litex/tools/litex_json2dts.py

   1 #!/usr/bin/env python3
   2
   3 # This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
   4 # This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
   5 # License: BSD
   6
   7 import sys
   8 import json
   9 import argparse
  10
  11
  12 def generate_dts(d):
  13
  14     kB = 1024
  15     mB = kB*1024
  16
  17     aliases = {}
  18
  19     # Header -------------------------------------------------------------------------------------------
  20
  21     dts = """
  22 /dts-v1/;
  23
  24 / {
  25         #address-cells = <1>;
  26         #size-cells    = <1>;
  27         compatible = "enjoy-digital,litex-vexriscv-soclinux";
  28         model = "VexRiscv SoCLinux";
  29
  30 """
  31
  32     # Boot Arguments -----------------------------------------------------------------------------------
  33
  34     dts += """
  35         chosen {{
  36                 bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi root=/dev/ram0 init=/sbin/init swiotlb=32";
  37                 linux,initrd-start = <0x{linux_initrd_start:x}>;
  38                 linux,initrd-end   = <0x{linux_initrd_end:x}>;
  39         }};
  40 """.format(main_ram_base=d["memories"]["main_ram"]["base"],
  41            main_ram_size=d["memories"]["main_ram"]["size"],
  42            main_ram_size_mb=d["memories"]["main_ram"]["size"] // mB,
  43            linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
  44            linux_initrd_end=d["memories"]["main_ram"]["base"] + 16*mB)
  45
  46     # CPU ----------------------------------------------------------------------------------------------
  47
  48     dts += """
  49         cpus {{
  50                 #address-cells = <1>;
  51                 #size-cells    = <0>;
  52                 timebase-frequency = <{sys_clk_freq}>;
  53                 cpu@0 {{
  54                         clock-frequency = <0x0>;
  55                         compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
  56                         d-cache-block-size = <0x40>;
  57                         d-cache-sets = <0x40>;
  58                         d-cache-size = <0x8000>;
  59                         d-tlb-sets = <0x1>;
  60                         d-tlb-size = <0x20>;
  61                         device_type = "cpu";
  62                         i-cache-block-size = <0x40>;
  63                         i-cache-sets = <0x40>;
  64                         i-cache-size = <0x8000>;
  65                         i-tlb-sets = <0x1>;
  66                         i-tlb-size = <0x20>;
  67                         mmu-type = "riscv,sv32";
  68                         reg = <0x0>;
  69                         riscv,isa = "rv32ima";
  70                         sifive,itim = <0x1>;
  71                         status = "okay";
  72                         tlb-split;
  73                 }};
  74         }};
  75 """.format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
  76
  77     # Memory -------------------------------------------------------------------------------------------
  78
  79     dts += """
  80         memory@{main_ram_base:x} {{
  81                 device_type = "memory";
  82                 reg = <0x{main_ram_base:x} 0x{main_ram_size:x}>;
  83         }};
  84 """.format(main_ram_base=d["memories"]["main_ram"]["base"],
  85            main_ram_size=d["memories"]["main_ram"]["size"])
  86
  87     if "emulator" in d["memories"]:
  88         dts += """
  89
  90         reserved-memory {{
  91                 #address-cells = <1>;
  92                 #size-cells    = <1>;
  93                 ranges;
  94                 vexriscv_emulator@{emulator_base:x} {{
  95                         reg = <0x{emulator_base:x} 0x{emulator_size:x}>;
  96                 }};
  97         }};
  98 """.format(emulator_base=d["memories"]["emulator"]["base"],
  99            emulator_size=d["memories"]["emulator"]["size"])
 100
 101     # SoC ----------------------------------------------------------------------------------------------
 102
 103     dts += """
 104         soc {
 105                 #address-cells = <1>;
 106                 #size-cells    = <1>;
 107                 compatible = "simple-bus";
 108                 ranges;
 109 """
 110
 111     # Interrupt controller -----------------------------------------------------------------------------
 112
 113     dts += """
 114                 intc0: interrupt-controller {
 115                         interrupt-controller;
 116                         #interrupt-cells = <1>;
 117                         compatible = "vexriscv,intc0";
 118                         status = "okay";
 119                 };
 120 """
 121
 122     # SoC Controller -----------------------------------------------------------------------------------
 123
 124     dts += """
 125                 soc_ctrl0: soc_controller@{soc_ctrl_csr_base:x} {{
 126                         compatible = "litex,soc_controller";
 127                         reg = <0x{soc_ctrl_csr_base:x} 0xc>;
 128                         status = "okay";
 129                 }};
 130 """.format(soc_ctrl_csr_base=d["csr_bases"]["ctrl"])
 131
 132     # UART ---------------------------------------------------------------------------------------------
 133
 134     if "uart" in d["csr_bases"]:
 135
 136         aliases["serial0"] = "liteuart0"
 137
 138         dts += """
 139                 liteuart0: serial@{uart_csr_base:x} {{
 140                         device_type = "serial";
 141                         compatible = "litex,liteuart";
 142                         reg = <0x{uart_csr_base:x} 0x100>;
 143                         status = "okay";
 144                 }};
 145 """.format(uart_csr_base=d["csr_bases"]["uart"])
 146
 147     # Ethernet MAC -------------------------------------------------------------------------------------
 148
 149     if "ethphy" in d["csr_bases"] and "ethmac" in d["csr_bases"]:
 150
 151         dts += """
 152                 mac0: mac@{ethmac_csr_base:x} {{
 153                         compatible = "litex,liteeth";
 154                         reg = <0x{ethmac_csr_base:x} 0x7c
 155                                 0x{ethphy_csr_base:x} 0x0a
 156                                 0x{ethmac_mem_base:x} 0x2000>;
 157                         tx-fifo-depth = <{ethmac_tx_slots}>;
 158                         rx-fifo-depth = <{ethmac_rx_slots}>;
 159                 }};
 160 """.format(ethphy_csr_base=d["csr_bases"]["ethphy"],
 161            ethmac_csr_base=d["csr_bases"]["ethmac"],
 162            ethmac_mem_base=d["memories"]["ethmac"]["base"],
 163            ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
 164            ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
 165
 166     # Leds ---------------------------------------------------------------------------------------------
 167
 168     if "leds" in d["csr_bases"]:
 169
 170         dts += """
 171                 leds: gpio@{leds_csr_base:x} {{
 172                         compatible = "litex,gpio";
 173                         reg = <0x{leds_csr_base:x} 0x4>;
 174                         litex,direction = "out";
 175                         status = "disabled";
 176                 }};
 177 """.format(leds_csr_base=d["csr_bases"]["leds"])
 178
 179     # RGB Led ------------------------------------------------------------------------------------------
 180
 181     for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
 182         if name in d["csr_bases"]:
 183
 184                 dts += """
 185                 {pwm_name}: pwm@{pwm_csr_base:x} {{
 186                         compatible = "litex,pwm";
 187                         reg = <0x{pwm_csr_base:x} 0x24>;
 188                         clock = <100000000>;
 189                         #pwm-cells = <3>;
 190                         status = "okay";
 191                 }};
 192 """.format(pwm_name=name,
 193            pwm_csr_base=d["csr_bases"][name])
 194
 195     # Switches -----------------------------------------------------------------------------------------
 196
 197     if "switches" in d["csr_bases"]:
 198
 199         dts += """
 200                 switches: gpio@{switches_csr_base:x} {{
 201                         compatible = "litex,gpio";
 202                         reg = <0x{switches_csr_base:x} 0x4>;
 203                         litex,direction = "in";
 204                         status = "disabled";
 205                 }};
 206 """.format(switches_csr_base=d["csr_bases"]["switches"])
 207
 208     # SPI ----------------------------------------------------------------------------------------------
 209
 210     if "spi" in d["csr_bases"]:
 211
 212         aliases["spi0"] = "litespi0"
 213
 214         dts += """
 215                 litespi0: spi@{spi_csr_base:x} {{
 216                         compatible = "litex,litespi";
 217                         reg = <0x{spi_csr_base:x} 0x100>;
 218                         status = "okay";
 219
 220                         litespi,max-bpw = <8>;
 221                         litespi,sck-frequency = <1000000>;
 222                         litespi,num-cs = <1>;
 223
 224                         #address-cells = <1>;
 225                         #size-cells    = <1>;
 226
 227                         spidev0: spidev@0 {{
 228                                 compatible = "linux,spidev";
 229                                 reg = <0>;
 230                                 spi-max-frequency = <1000000>;
 231                                 status = "okay";
 232                         }};
 233                 }};
 234 """.format(spi_csr_base=d["csr_bases"]["spi"])
 235
 236     # SPIFLASH -------------------------------------------------------------------------------------------
 237
 238     if "spiflash" in d["csr_bases"]:
 239
 240         aliases["spiflash"] = "litespiflash"
 241
 242         dts += """
 243                 litespiflash: spiflash@{spiflash_csr_base:x} {{
 244                             #address-cells = <1>;
 245                             #size-cells    = <1>;
 246                         compatible = "litex,spiflash";
 247                         reg = <0x{spiflash_csr_base:x} 0x100>;
 248                         flash: flash@0 {{
 249                                 compatible = "jedec,spi-nor";
 250                                 reg = <0x0 0x{spiflash_size:x}>;
 251                         }};
 252                 }};
 253 """.format(spiflash_csr_base=d["csr_bases"]["spiflash"],
 254            spiflash_size=d["memories"]["spiflash"]["size"])
 255
 256     # SPISDCARD ----------------------------------------------------------------------------------------
 257
 258     if "spisdcard" in d["csr_bases"]:
 259
 260         aliases["sdcard0"] = "litespisdcard0"
 261
 262         dts += """
 263                 litespisdcard0: spi@{spisdcard_csr_base:x} {{
 264                         compatible = "litex,litespi";
 265                         reg = <0x{spisdcard_csr_base:x} 0x100>;
 266                         status = "okay";
 267
 268                         litespi,max-bpw = <8>;
 269                         litespi,sck-frequency = <1500000>;
 270                         litespi,num-cs = <1>;
 271
 272                         #address-cells = <1>;
 273                         #size-cells    = <1>;
 274
 275                         mmc-slot@0 {{
 276                                 compatible = "mmc-spi-slot";
 277                             reg = <0>;
 278                                 voltage-ranges = <3300 3300>;
 279                                 spi-max-frequency = <1500000>;
 280                             status = "okay";
 281                         }};
 282                 }};
 283 """.format(spisdcard_csr_base=d["csr_bases"]["spisdcard"])
 284
 285     # I2C ----------------------------------------------------------------------------------------------
 286
 287     if "i2c0" in d["csr_bases"]:
 288
 289         dts += """
 290                 i2c0: i2c@{i2c0_csr_base:x} {{
 291                         compatible = "litex,i2c";
 292                         reg = <0x{i2c0_csr_base:x} 0x5>;
 293                         status = "okay";
 294                 }};
 295 """.format(i2c0_csr_base=d["csr_bases"]["i2c0"])
 296
 297     # XADC ---------------------------------------------------------------------------------------------
 298
 299     if "xadc" in d["csr_bases"]:
 300
 301         dts += """
 302                 hwmon0: xadc@{xadc_csr_base:x} {{
 303                         compatible = "litex,hwmon-xadc";
 304                         reg = <0x{xadc_csr_base:x} 0x20>;
 305                         status = "okay";
 306                 }};
 307 """.format(xadc_csr_base=d["csr_bases"]["xadc"])
 308
 309     # Framebuffer --------------------------------------------------------------------------------------
 310
 311     if "framebuffer" in d["csr_bases"]:
 312
 313         # FIXME: dynamic framebuffer base and size
 314         framebuffer_base   = 0xc8000000
 315         framebuffer_width  = d["constants"]["litevideo_h_active"]
 316         framebuffer_height = d["constants"]["litevideo_v_active"]
 317         dts += """
 318                 framebuffer0: framebuffer@f0000000 {{
 319                         compatible = "simple-framebuffer";
 320                         reg = <0x{framebuffer_base:x} 0x{framebuffer_size:x}>;
 321                         width = <{framebuffer_width}>;
 322                         height = <{framebuffer_height}>;
 323                         stride = <{framebuffer_stride}>;
 324                         format = "a8b8g8r8";
 325                 }};
 326 """.format(framebuffer_base=framebuffer_base,
 327            framebuffer_width=framebuffer_width,
 328            framebuffer_height=framebuffer_height,
 329            framebuffer_size=framebuffer_width * framebuffer_height * 4,
 330            framebuffer_stride=framebuffer_width * 4)
 331
 332         dts += """
 333                 litevideo0: gpu@{litevideo_base:x} {{
 334                         compatible = "litex,litevideo";
 335                         reg = <0x{litevideo_base:x} 0x100>;
 336                         litevideo,pixel-clock = <{litevideo_pixel_clock}>;
 337                         litevideo,h-active = <{litevideo_h_active}>;
 338                         litevideo,h-blanking = <{litevideo_h_blanking}>;
 339                         litevideo,h-sync = <{litevideo_h_sync}>;
 340                         litevideo,h-front-porch = <{litevideo_h_front_porch}>;
 341                         litevideo,v-active = <{litevideo_v_active}>;
 342                         litevideo,v-blanking = <{litevideo_v_blanking}>;
 343                         litevideo,v-sync = <{litevideo_v_sync}>;
 344                         litevideo,v-front-porch = <{litevideo_v_front_porch}>;
 345                         litevideo,dma-offset = <0x{litevideo_dma_offset:x}>;
 346                         litevideo,dma-length = <0x{litevideo_dma_length:x}>;
 347                 }};
 348 """.format(litevideo_base=d["csr_bases"]["framebuffer"],
 349            litevideo_pixel_clock=int(d["constants"]["litevideo_pix_clk"] / 1e3),
 350            litevideo_h_active=d["constants"]["litevideo_h_active"],
 351            litevideo_h_blanking=d["constants"]["litevideo_h_blanking"],
 352            litevideo_h_sync=d["constants"]["litevideo_h_sync"],
 353            litevideo_h_front_porch=d["constants"]["litevideo_h_front_porch"],
 354            litevideo_v_active=d["constants"]["litevideo_v_active"],
 355            litevideo_v_blanking=d["constants"]["litevideo_v_blanking"],
 356            litevideo_v_sync=d["constants"]["litevideo_v_sync"],
 357            litevideo_v_front_porch=d["constants"]["litevideo_v_front_porch"],
 358            litevideo_dma_offset=framebuffer_base - d["memories"]["main_ram"]["base"],
 359            litevideo_dma_length=framebuffer_width * framebuffer_height * 4)
 360
 361     # ICAPBitstream ------------------------------------------------------------------------------------
 362
 363     if "icap_bit" in d["csr_bases"]:
 364
 365         dts += """
 366                 fpga0: icap@{icap_csr_base:x} {{
 367                         compatible = "litex,fpga-icap";
 368                         reg = <0x{icap_csr_base:x} 0x14>;
 369                         status = "okay";
 370                 }};
 371 """.format(icap_csr_base=d["csr_bases"]["icap_bit"])
 372
 373     # CLK ----------------------------------------------------------------------------------------------
 374
 375     def add_clkout(clkout_nr, clk_f, clk_p, clk_dn, clk_dd, clk_margin, clk_margin_exp):
 376         return """
 377                         CLKOUT{clkout_nr}: CLKOUT{clkout_nr} {{
 378                                 compatible = "litex,clk";
 379                                 #clock-cells =  <0>;
 380                                 clock-output-names = "CLKOUT{clkout_nr}";
 381                                 reg = <{clkout_nr}>;
 382                                 litex,clock-frequency = <{clk_f}>;
 383                                 litex,clock-phase = <{clk_p}>;
 384                                 litex,clock-duty-num = <{clk_dn}>;
 385                                 litex,clock-duty-den = <{clk_dd}>;
 386                                 litex,clock-margin = <{clk_margin}>;
 387                                 litex,clock-margin-exp = <{clk_margin_exp}>;
 388                         }};
 389 """.format(clkout_nr=clkout_nr,
 390            clk_f=clk_f,
 391            clk_p=clk_p,
 392            clk_dn=clk_dn,
 393            clk_dd=clk_dd,
 394            clk_margin=clk_margin,
 395            clk_margin_exp=clk_margin_exp)
 396
 397     if "mmcm" in d["csr_bases"]:
 398         nclkout = d["constants"]["nclkout"]
 399
 400         dts += """
 401                 clk0: clk@{mmcm_csr_base:x} {{
 402                         compatible = "litex,clk";
 403                         reg = <0x{mmcm_csr_base:x} 0x100>;
 404                         #clock-cells = <1>;
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         clock-output-names =
 408 """.format(mmcm_csr_base=d["csr_bases"]["mmcm"])
 409
 410         for clkout_nr in range(nclkout - 1):
 411
 412             dts += """
 413                                 "CLKOUT{clkout_nr}",
 414 """.format(clkout_nr=clkout_nr)
 415
 416         dts += """
 417                                 "CLKOUT{nclkout}";
 418 """.format(nclkout=(nclkout - 1))
 419
 420         dts += """
 421                         litex,lock-timeout = <{mmcm_lock_timeout}>;
 422                         litex,drdy-timeout = <{mmcm_drdy_timeout}>;
 423                         litex,sys-clock-frequency = <{sys_clk}>;
 424                         litex,divclk-divide-min = <{divclk_divide_range[0]}>;
 425                         litex,divclk-divide-max = <{divclk_divide_range[1]}>;
 426                         litex,clkfbout-mult-min = <{clkfbout_mult_frange[0]}>;
 427                         litex,clkfbout-mult-max = <{clkfbout_mult_frange[1]}>;
 428                         litex,vco-freq-min = <{vco_freq_range[0]}>;
 429                         litex,vco-freq-max = <{vco_freq_range[1]}>;
 430                         litex,clkout-divide-min = <{clkout_divide_range[0]}>;
 431                         litex,clkout-divide-max = <{clkout_divide_range[1]}>;
 432                         litex,vco-margin = <{vco_margin}>;
 433 """.format(mmcm_lock_timeout=d["constants"]["mmcm_lock_timeout"],
 434            mmcm_drdy_timeout=d["constants"]["mmcm_drdy_timeout"],
 435            sys_clk=d["constants"]["config_clock_frequency"],
 436            divclk_divide_range=(d["constants"]["divclk_divide_range_min"], d["constants"]["divclk_divide_range_max"]),
 437            clkfbout_mult_frange=(d["constants"]["clkfbout_mult_frange_min"], d["constants"]["clkfbout_mult_frange_max"]),
 438            vco_freq_range=(d["constants"]["vco_freq_range_min"], d["constants"]["vco_freq_range_max"]),
 439            clkout_divide_range=(d["constants"]["clkout_divide_range_min"], d["constants"]["clkout_divide_range_max"]),
 440            vco_margin=d["constants"]["vco_margin"])
 441
 442         for clkout_nr in range(nclkout):
 443             dts += add_clkout(clkout_nr,
 444                               d["constants"]["clkout_def_freq"],
 445                               d["constants"]["clkout_def_phase"],
 446                               d["constants"]["clkout_def_duty_num"],
 447                               d["constants"]["clkout_def_duty_den"],
 448                               d["constants"]["clkout_margin"],
 449                               d["constants"]["clkout_margin_exp"])
 450
 451         dts += """
 452                 };"""
 453
 454     # SDCARD -------------------------------------------------------------------------------------------
 455
 456     if "sdcore" in d["csr_bases"]:
 457
 458         dts += """
 459                 mmc0: mmc@{mmc_csr_base:x} {{
 460                         compatible = "litex,mmc";
 461                         bus-width = <4>;
 462                         reg = <
 463                                 0x{sdphy_csr_base:x} 0x100
 464                                 0x{sdcore_csr_base:x} 0x100
 465                         >;
 466                         status = "okay";
 467                 }};
 468 """.format(mmc_csr_base=d["csr_bases"]["sdcore"],
 469            sdphy_csr_base=d["csr_bases"]["sdphy"],
 470            sdcore_csr_base=d["csr_bases"]["sdcore"])
 471
 472     dts += """
 473         };
 474 """
 475
 476     # Aliases ------------------------------------------------------------------------------------------
 477
 478     if aliases:
 479         dts += """
 480         aliases {
 481 """
 482         for alias in aliases:
 483
 484             dts += """
 485                 {} = &{};
 486 """.format(alias, aliases[alias])
 487
 488         dts += """
 489         };
 490 """
 491
 492     dts += """
 493 };
 494 """
 495
 496     # Leds & switches ----------------------------------------------------------------------------------
 497
 498     if "leds" in d["csr_bases"]:
 499         dts += """
 500 &leds {
 501         litex,ngpio = <4>;
 502         status = "okay";
 503 };
 504 """
 505
 506     if "switches" in d["csr_bases"]:
 507         dts += """
 508 &switches {
 509         litex,ngpio = <4>;
 510         status = "okay";
 511 };
 512 """
 513
 514     return dts
 515
 516
 517 def main():
 518     parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
 519     parser.add_argument("csr_json", help="CSR JSON file")
 520     args = parser.parse_args()
 521
 522     d = json.load(open(args.csr_json))
 523
 524     print(generate_dts(d))
 525
 526
 527 if __name__ == "__main__":
 528     main()