lkcl.mdwn

   1 # Luke Kenneth Casson Leighton
   2
   3 Lead dev and Project Coordinator for Libre-SOC.
   4
   5 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
   6 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
   7 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
   8 * <http://twitter.com/lkcl>
   9
  10 # Status tracking
  11
  12 move things along from one stage to the next
  13
  14 ## Currently working on
  15
  16  - Project Management
  17  - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
  18  - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
  19  - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  20  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
  21  - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  22  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  23  - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  24  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  25  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  26  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  27  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  28  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
  29  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
  30    - EUR
  31  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  32  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  33  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
  34  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  35  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  36  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
  37  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  38  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  39  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
  40  - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
  41    - shared with cole
  42  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
  43    - EUR 50, shared with samuel 10%
  44  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  45  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
  46  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  47  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
  48    - EUR 50, shared with samuel (EUR 350)
  49  - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
  50  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  51  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  52  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
  53  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  54  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
  55    - EUR 200
  56  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
  57  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
  58    - donated
  59    - parent #198
  60    - EUR 200
  61  - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
  62   - MultiCompUnit (and Function Units) proof
  63  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
  64   - donated
  65   - parent #195
  66  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
  67
  68 ## Completed but not yet submitted:
  69  - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
  70  - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
  71    - EUR 1600
  72  - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
  73    - EUR 600
  74  - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
  75    - EUR 500
  76  - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  77  - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
  78  - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
  79  - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
  80  - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  81
  82
  83  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
  84    - EUR 150
  85    - donated
  86  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
  87    - EUR 200
  88    - donated
  89  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
  90    - EUR 150
  91    - donated
  92  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
  93    - EUR 200
  94    - donated
  95  - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
  96    - EUR 700
  97    - (lip6.fr donated)
  98  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
  99    - (total EUR 400 25% donated by LIP6)
 100    - EUR 100 lkcl
 101  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
 102    - EUR 900
 103    - shared with [[lxo]]
 104  - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
 105    - EUR 1100
 106    - shared with lauri, jacob
 107  - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
 108    - EUR 1250
 109    - Shared 50% with Staf
 110  - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
 111    - EUR 300
 112    - Shared with Staf, cole
 113  - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
 114    - EUR 450
 115    - Shared with Staf
 116  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
 117  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 118    - EUR 3000
 119    - shared with Staf 50%
 120  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
 121    - Project 2019-10-043 06dec2020 wishbone
 122    - EUR (TBD)
 123
 124 ### Project 2019-10-029 14mar2020 coriolis2
 125
 126  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
 127    - (total EUR 100 shared 50% with staf)
 128    - EUR 50 lkcl
 129  - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
 130    - (total EUR 1500 shared 50% with LIP6)
 131    - EUR 750 lkcl
 132  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
 133    - (total EUR 400 shared 75% with LIP6)
 134    - EUR 300 lkcl
 135
 136 ### Project 2019-02-012 06dec2020 Core
 137
 138  - <https://bugs.libre-soc.org/show_bug.cgi?id=538> pipeline API continued
 139    - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
 140  - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
 141    - EUR 750 donated
 142  - <https://bugs.libre-soc.org/show_bug.cgi?id=94> LDST Dep Matrix
 143    - EUR 1500
 144
 145 ### Project 2019-10-043 06dec2020 wishbone
 146
 147  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
 148    - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
 149  - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 150    - EUR 200
 151  - <https://bugs.libre-soc.org/show_bug.cgi?id=426> LD/ST sign-extend
 152    - EUR 100
 153  - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
 154    - EUR 200
 155  - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 156    - EUR 100
 157  - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
 158    - EUR 200
 159  - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
 160    - EUR 450
 161  - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 162    - EUR 100
 163  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
 164    - EUR 200 donated
 165  - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
 166    - EUR 250 (share with cole)
 167
 168 ### Project 2019-10-032 06dec2020 proofs
 169
 170  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> POWER9 ALU proof
 171    - parent #195
 172    - EUR 400 donated
 173  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> POWER9 CR proof
 174    - parent #195
 175    - EUR 300 donated
 176  - <https://bugs.libre-soc.org/show_bug.cgi?id=335> POWER9 BRANCH proof
 177    - EUR 400 donated
 178    - parent #195
 179  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> POWER9 LOGICAL proof
 180    - EUR 400 donated
 181    - parent #195
 182
 183 ## Submitted for NLNet RFP
 184
 185 submitted but not confirmed paid:
 186
 187  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
 188
 189 ### Project 2019-02-012 04sep2020 Core
 190
 191  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
 192    - EUR 2000 total, shared with florent.  EUR 1200
 193
 194 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 195
 196 ## Paid
 197
 198 donation from NLNet confirmed received:
 199
 200 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER
 201
 202  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
 203     - EUR 2000, python POWER9 simulator
 204     - Shared 50% with [[mnolan]], EUR 1000
 205  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
 206     - EUR 250, functions needed for simulator
 207     - Shared 20% with [[mnolan]], EUR 50
 208
 209 ### proofs 2019-10-032
 210
 211  - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
 212    - EUR 500 shared 20% samuel, EUR 100
 213  - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
 214    - EUR 300 shared 1/6 [[mnolan]] EUR 50
 215  - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
 216    - EUR 400 shared 25% [[mnolan]] EUR 100
 217  - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
 218    - EUR 150
 219
 220 ### wishbone 2019-10-043
 221
 222  - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
 223    - EUR 500
 224  - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
 225     - EUR 300
 226  - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
 227     - EUR 250
 228  - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
 229    - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
 230  - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
 231    - EUR 300
 232  - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
 233    - EUR 400, 50% shared [[programmerjake]] EUR 200
 234  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
 235    - EUR 750, 33% shared [[programmerjake]] EUR 250
 236  - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
 237    - EUR 200 50% shared, cole, EUR 100
 238  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
 239    - EUR 200
 240  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
 241    - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
 242  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 243    - EUR 150
 244  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
 245    - EUR 400 shared 50% [[mnolan]] EUR 200
 246  - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
 247    - EUR 250 shared 40% [[mnolan]] EUR 100
 248  - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
 249    - EUR 300 shared 1/3 [[mnolan]] EUR 100
 250  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
 251    - EUR 300 shared 50% [[mnolan]] EUR 150
 252  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
 253    - EUR 750
 254  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
 255   - EUR 100
 256  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 257   - EUR 100
 258  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
 259    - EUR 100
 260  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 261    - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
 262
 263 ### Project 2019-02-012 28-apr-2020
 264
 265  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
 266    - 6600 scoreboard multi-read/write
 267    - EUR 600
 268  - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
 269    - Partitioned equals and greater than comparison
 270    - Shared 50% with [[mnolan]]
 271    - EUR 200 (each)
 272  - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
 273    - partitioned scalar/vector shift
 274    - Shared 50% with [[lkcl]]
 275    - EUR 350 (each)
 276
 277 ### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER
 278
 279  - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
 280     - auto-parser of POWER9
 281     - Shared 50% with [[mnolan]]
 282     - EUR 500 (each)
 283
 284 ### Project 2019-10-029 Date 14mar2020
 285
 286 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
 287   - EUR 1200
 288
 289 ### Project 2019-02-012 Date 12mar2020
 290
 291 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
 292 * <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
 293 * <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
 294 * <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
 295
 296 ### Project 2019-02-012 Date 28jan2020
 297
 298 * admin tasks
 299 * <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
 300