2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
8 use work.insn_helpers.all;
12 -- We calculate the address in the first cycle
16 HAS_FPU : boolean := true;
17 -- Non-zero to enable log data collection
18 LOG_LENGTH : natural := 0
24 l_in : in Execute1ToLoadstore1Type;
25 e_out : out Loadstore1ToExecute1Type;
26 l_out : out Loadstore1ToWritebackType;
28 d_out : out Loadstore1ToDcacheType;
29 d_in : in DcacheToLoadstore1Type;
31 m_out : out Loadstore1ToMmuType;
32 m_in : in MmuToLoadstore1Type;
34 dc_stall : in std_ulogic;
36 log_out : out std_ulogic_vector(9 downto 0)
40 architecture behave of loadstore1 is
42 -- State machine for unaligned loads/stores
43 type state_t is (IDLE, -- ready for instruction
44 MMU_LOOKUP, -- waiting for MMU to look up translation
45 TLBIE_WAIT, -- waiting for MMU to finish doing a tlbie
46 FINISH_LFS -- write back converted SP data for lfs*
49 type byte_index_t is array(0 to 7) of unsigned(2 downto 0);
50 subtype byte_trim_t is std_ulogic_vector(1 downto 0);
51 type trim_ctl_t is array(0 to 7) of byte_trim_t;
53 type request_t is record
60 read_spr : std_ulogic;
61 write_spr : std_ulogic;
63 instr_fault : std_ulogic;
64 load_zero : std_ulogic;
65 do_update : std_ulogic;
67 mode_32bit : std_ulogic;
68 addr : std_ulogic_vector(63 downto 0);
69 addr0 : std_ulogic_vector(63 downto 0);
70 byte_sel : std_ulogic_vector(7 downto 0);
71 second_bytes : std_ulogic_vector(7 downto 0);
72 store_data : std_ulogic_vector(63 downto 0);
73 instr_tag : instr_tag_t;
74 write_reg : gspr_index_t;
75 length : std_ulogic_vector(3 downto 0);
76 elt_length : std_ulogic_vector(3 downto 0);
77 byte_reverse : std_ulogic;
78 brev_mask : unsigned(2 downto 0);
79 sign_extend : std_ulogic;
84 atomic_last : std_ulogic;
86 nc : std_ulogic; -- non-cacheable access
87 virt_mode : std_ulogic;
88 priv_mode : std_ulogic;
90 sprn : std_ulogic_vector(9 downto 0);
91 is_slbia : std_ulogic;
92 align_intr : std_ulogic;
93 dword_index : std_ulogic;
94 two_dwords : std_ulogic;
95 nia : std_ulogic_vector(63 downto 0);
97 constant request_init : request_t := (valid => '0', dc_req => '0', load => '0', store => '0', tlbie => '0',
98 dcbz => '0', read_spr => '0', write_spr => '0', mmu_op => '0',
99 instr_fault => '0', load_zero => '0', do_update => '0', noop => '0',
100 mode_32bit => '0', addr => (others => '0'), addr0 => (others => '0'),
101 byte_sel => x"00", second_bytes => x"00",
102 store_data => (others => '0'), instr_tag => instr_tag_init,
103 write_reg => 7x"00", length => x"0",
104 elt_length => x"0", byte_reverse => '0', brev_mask => "000",
105 sign_extend => '0', update => '0',
106 xerc => xerc_init, reserve => '0',
107 atomic => '0', atomic_last => '0', rc => '0', nc => '0',
108 virt_mode => '0', priv_mode => '0', load_sp => '0',
109 sprn => 10x"0", is_slbia => '0', align_intr => '0',
110 dword_index => '0', two_dwords => '0',
111 nia => (others => '0'));
113 type reg_stage1_t is record
118 type reg_stage2_t is record
120 byte_index : byte_index_t;
121 use_second : std_ulogic_vector(7 downto 0);
122 wait_dc : std_ulogic;
123 wait_mmu : std_ulogic;
124 one_cycle : std_ulogic;
125 wr_sel : std_ulogic_vector(1 downto 0);
128 type reg_stage3_t is record
130 instr_tag : instr_tag_t;
131 write_enable : std_ulogic;
132 write_reg : gspr_index_t;
133 write_data : std_ulogic_vector(63 downto 0);
136 store_done : std_ulogic;
137 convert_lfs : std_ulogic;
138 load_data : std_ulogic_vector(63 downto 0);
139 dar : std_ulogic_vector(63 downto 0);
140 dsisr : std_ulogic_vector(31 downto 0);
141 ld_sp_data : std_ulogic_vector(31 downto 0);
142 ld_sp_nz : std_ulogic;
143 ld_sp_lz : std_ulogic_vector(5 downto 0);
144 stage1_en : std_ulogic;
145 interrupt : std_ulogic;
146 intr_vec : integer range 0 to 16#fff#;
147 nia : std_ulogic_vector(63 downto 0);
148 srr1 : std_ulogic_vector(15 downto 0);
151 signal req_in : request_t;
152 signal r1, r1in : reg_stage1_t;
153 signal r2, r2in : reg_stage2_t;
154 signal r3, r3in : reg_stage3_t;
156 signal busy : std_ulogic;
157 signal complete : std_ulogic;
158 signal flushing : std_ulogic;
160 signal store_sp_data : std_ulogic_vector(31 downto 0);
161 signal load_dp_data : std_ulogic_vector(63 downto 0);
162 signal store_data : std_ulogic_vector(63 downto 0);
164 signal stage1_issue_enable : std_ulogic;
165 signal stage1_req : request_t;
166 signal stage1_dcreq : std_ulogic;
167 signal stage1_dreq : std_ulogic;
168 signal stage2_busy_next : std_ulogic;
169 signal stage3_busy_next : std_ulogic;
171 -- Generate byte enables from sizes
172 function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
186 end function length_to_sel;
188 -- Calculate byte enables
189 -- This returns 16 bits, giving the select signals for two transfers,
190 -- to account for unaligned loads or stores
191 function xfer_data_sel(size : in std_logic_vector(3 downto 0);
192 address : in std_logic_vector(2 downto 0))
193 return std_ulogic_vector is
194 variable longsel : std_ulogic_vector(15 downto 0);
196 longsel := "00000000" & length_to_sel(size);
197 return std_ulogic_vector(shift_left(unsigned(longsel),
198 to_integer(unsigned(address))));
199 end function xfer_data_sel;
201 -- 23-bit right shifter for DP -> SP float conversions
202 function shifter_23r(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
203 return std_ulogic_vector is
204 variable fs1 : std_ulogic_vector(22 downto 0);
205 variable fs2 : std_ulogic_vector(22 downto 0);
207 case shift(1 downto 0) is
211 fs1 := '0' & frac(22 downto 1);
213 fs1 := "00" & frac(22 downto 2);
215 fs1 := "000" & frac(22 downto 3);
217 case shift(4 downto 2) is
221 fs2 := x"0" & fs1(22 downto 4);
223 fs2 := x"00" & fs1(22 downto 8);
225 fs2 := x"000" & fs1(22 downto 12);
227 fs2 := x"0000" & fs1(22 downto 16);
229 fs2 := x"00000" & fs1(22 downto 20);
234 -- 23-bit left shifter for SP -> DP float conversions
235 function shifter_23l(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
236 return std_ulogic_vector is
237 variable fs1 : std_ulogic_vector(22 downto 0);
238 variable fs2 : std_ulogic_vector(22 downto 0);
240 case shift(1 downto 0) is
244 fs1 := frac(21 downto 0) & '0';
246 fs1 := frac(20 downto 0) & "00";
248 fs1 := frac(19 downto 0) & "000";
250 case shift(4 downto 2) is
254 fs2 := fs1(18 downto 0) & x"0" ;
256 fs2 := fs1(14 downto 0) & x"00";
258 fs2 := fs1(10 downto 0) & x"000";
260 fs2 := fs1(6 downto 0) & x"0000";
262 fs2 := fs1(2 downto 0) & x"00000";
268 loadstore1_reg: process(clk)
270 if rising_edge(clk) then
278 r3.write_enable <= '0';
281 r3.convert_lfs <= '0';
287 flushing <= (flushing or (r1in.req.valid and r1in.req.align_intr)) and
290 stage1_dreq <= stage1_dcreq;
291 if d_in.valid = '1' then
292 assert r2.req.valid = '1' and r2.req.dc_req = '1' and r3.state = IDLE severity failure;
294 if d_in.error = '1' then
295 assert r2.req.valid = '1' and r2.req.dc_req = '1' and r3.state = IDLE severity failure;
297 if m_in.done = '1' or m_in.err = '1' then
298 assert r2.req.valid = '1' and (r3.state = MMU_LOOKUP or r3.state = TLBIE_WAIT) severity failure;
303 ls_fp_conv: if HAS_FPU generate
304 -- Convert DP data to SP for stfs
305 dp_to_sp: process(all)
306 variable exp : unsigned(10 downto 0);
307 variable frac : std_ulogic_vector(22 downto 0);
308 variable shift : unsigned(4 downto 0);
310 store_sp_data(31) <= l_in.data(63);
311 store_sp_data(30 downto 0) <= (others => '0');
312 exp := unsigned(l_in.data(62 downto 52));
314 store_sp_data(30) <= l_in.data(62);
315 store_sp_data(29 downto 0) <= l_in.data(58 downto 29);
316 elsif exp >= 874 then
317 -- denormalization required
318 frac := '1' & l_in.data(51 downto 30);
319 shift := 0 - exp(4 downto 0);
320 store_sp_data(22 downto 0) <= shifter_23r(frac, shift);
324 -- Convert SP data to DP for lfs
325 sp_to_dp: process(all)
326 variable exp : unsigned(7 downto 0);
327 variable exp_dp : unsigned(10 downto 0);
328 variable exp_nz : std_ulogic;
329 variable exp_ao : std_ulogic;
330 variable frac : std_ulogic_vector(22 downto 0);
331 variable frac_shift : unsigned(4 downto 0);
333 frac := r3.ld_sp_data(22 downto 0);
334 exp := unsigned(r3.ld_sp_data(30 downto 23));
335 exp_nz := or (r3.ld_sp_data(30 downto 23));
336 exp_ao := and (r3.ld_sp_data(30 downto 23));
337 frac_shift := (others => '0');
339 exp_dp := to_unsigned(2047, 11); -- infinity or NaN
340 elsif exp_nz = '1' then
341 exp_dp := 896 + resize(exp, 11); -- finite normalized value
342 elsif r3.ld_sp_nz = '0' then
343 exp_dp := to_unsigned(0, 11); -- zero
345 -- denormalized SP operand, need to normalize
346 exp_dp := 896 - resize(unsigned(r3.ld_sp_lz), 11);
347 frac_shift := unsigned(r3.ld_sp_lz(4 downto 0)) + 1;
349 load_dp_data(63) <= r3.ld_sp_data(31);
350 load_dp_data(62 downto 52) <= std_ulogic_vector(exp_dp);
351 load_dp_data(51 downto 29) <= shifter_23l(frac, frac_shift);
352 load_dp_data(28 downto 0) <= (others => '0');
356 -- Translate a load/store instruction into the internal request format
357 -- XXX this should only depend on l_in, but actually depends on
358 -- r1.req.addr0 as well (in the l_in.second = 1 case).
359 loadstore1_in: process(all)
360 variable v : request_t;
361 variable lsu_sum : std_ulogic_vector(63 downto 0);
362 variable brev_lenm1 : unsigned(2 downto 0);
363 variable long_sel : std_ulogic_vector(15 downto 0);
364 variable addr : std_ulogic_vector(63 downto 0);
365 variable sprn : std_ulogic_vector(9 downto 0);
366 variable misaligned : std_ulogic;
367 variable addr_mask : std_ulogic_vector(2 downto 0);
370 sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
372 v.valid := l_in.valid;
373 v.instr_tag := l_in.instr_tag;
374 v.mode_32bit := l_in.mode_32bit;
375 v.write_reg := l_in.write_reg;
376 v.length := l_in.length;
377 v.elt_length := l_in.length;
378 v.byte_reverse := l_in.byte_reverse;
379 v.sign_extend := l_in.sign_extend;
380 v.update := l_in.update;
382 v.reserve := l_in.reserve;
385 v.virt_mode := l_in.virt_mode;
386 v.priv_mode := l_in.priv_mode;
390 lsu_sum := std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2));
392 if HAS_FPU and l_in.is_32bit = '1' then
393 v.store_data := x"00000000" & store_sp_data;
395 v.store_data := l_in.data;
400 if l_in.second = '1' then
401 if l_in.update = '0' then
402 -- for the second half of a 16-byte transfer,
403 -- use the previous address plus 8.
404 addr := std_ulogic_vector(unsigned(r1.req.addr0(63 downto 3)) + 1) & r1.req.addr0(2 downto 0);
406 -- for an update-form load, use the previous address
407 -- as the value to write back to RA.
408 addr := r1.req.addr0;
411 if l_in.mode_32bit = '1' then
412 addr(63 downto 32) := (others => '0');
417 -- XXX Temporary hack. Mark the op as non-cachable if the address
418 -- is the form 0xc------- for a real-mode access.
419 if addr(31 downto 28) = "1100" and l_in.virt_mode = '0' then
423 addr_mask := std_ulogic_vector(unsigned(l_in.length(2 downto 0)) - 1);
425 -- Do length_to_sel and work out if we are doing 2 dwords
426 long_sel := xfer_data_sel(v.length, addr(2 downto 0));
427 v.byte_sel := long_sel(7 downto 0);
428 v.second_bytes := long_sel(15 downto 8);
429 if long_sel(15 downto 8) /= "00000000" then
433 -- check alignment for larx/stcx
434 misaligned := or (addr_mask and addr(2 downto 0));
435 v.align_intr := l_in.reserve and misaligned;
436 if l_in.repeat = '1' and l_in.second = '0' and l_in.update = '0' and addr(3) = '1' then
437 -- length is really 16 not 8
438 -- Make misaligned lq cause an alignment interrupt in LE mode,
439 -- in order to avoid the case with RA = RT + 1 where the second half
440 -- faults but the first doesn't (and updates RT+1, destroying RA).
441 -- The equivalent BE case doesn't occur because RA = RT is illegal.
443 if l_in.reserve = '1' or (l_in.op = OP_LOAD and l_in.byte_reverse = '0') then
448 v.atomic := not misaligned;
449 v.atomic_last := not misaligned and (l_in.second or not l_in.repeat);
455 if l_in.update = '0' or l_in.second = '0' then
457 if HAS_FPU and l_in.is_32bit = '1' then
458 -- Allow an extra cycle for SP->DP precision conversion
462 -- write back address to RA
467 v.align_intr := v.nc;
470 v.addr := l_in.addr2; -- address from RB for tlbie
471 v.is_slbia := l_in.insn(7);
477 v.mmu_op := sprn(9) or sprn(5);
478 when OP_FETCH_FAILED =>
479 -- send it to the MMU to do the radix walk
480 v.instr_fault := '1';
485 v.dc_req := l_in.valid and (v.load or v.store or v.dcbz) and not v.align_intr;
487 -- Work out controls for load and store formatting
489 if v.byte_reverse = '1' then
490 brev_lenm1 := unsigned(v.length(2 downto 0)) - 1;
492 v.brev_mask := brev_lenm1;
497 --busy <= r1.req.valid and ((r1.req.dc_req and not r1.issued) or
498 -- (r1.issued and d_in.error) or
499 -- stage2_busy_next or
500 -- (r1.req.dc_req and r1.req.two_dwords and not r1.req.dword_index));
501 complete <= r2.one_cycle or (r2.wait_dc and d_in.valid) or
502 (r2.wait_mmu and m_in.done) or r3.convert_lfs;
503 busy <= r1.req.valid or (r2.req.valid and not complete);
505 stage1_issue_enable <= r3.stage1_en and not (r1.req.valid and r1.req.mmu_op) and
506 not (r2.req.valid and r2.req.mmu_op);
508 -- Processing done in the first cycle of a load/store instruction
509 loadstore1_1: process(all)
510 variable v : reg_stage1_t;
511 variable req : request_t;
512 variable dcreq : std_ulogic;
513 variable addr : std_ulogic_vector(63 downto 0);
518 if flushing = '1' then
519 -- Make this a no-op request rather than simply invalid.
520 -- It will never get to stage 3 since there is a request ahead of
521 -- it with align_intr = 1.
525 -- Note that l_in.valid is gated with busy inside execute1
526 if l_in.valid = '1' then
527 dcreq := req.dc_req and stage1_issue_enable and not d_in.error and not dc_stall;
530 elsif r1.req.valid = '1' then
531 if r1.req.dc_req = '1' and r1.issued = '0' then
533 dcreq := stage1_issue_enable and not dc_stall and not d_in.error;
535 elsif r1.issued = '1' and d_in.error = '1' then
537 elsif stage2_busy_next = '0' then
538 -- we can change what's in r1 next cycle because the current thing
539 -- in r1 will go into r2
540 if r1.req.dc_req = '1' and r1.req.two_dwords = '1' and r1.req.dword_index = '0' then
541 -- construct the second request for a misaligned access
542 v.req.dword_index := '1';
543 v.req.addr := std_ulogic_vector(unsigned(r1.req.addr(63 downto 3)) + 1) & "000";
544 if r1.req.mode_32bit = '1' then
545 v.req.addr(32) := '0';
547 v.req.byte_sel := r1.req.second_bytes;
548 v.issued := stage1_issue_enable and not dc_stall;
549 dcreq := stage1_issue_enable and not dc_stall;
556 if r3in.interrupt = '1' then
562 stage1_dcreq <= dcreq;
566 -- Processing done in the second cycle of a load/store instruction.
567 -- Store data is formatted here and sent to the dcache.
568 -- The request in r1 is sent to stage 3 if stage 3 will not be busy next cycle.
569 loadstore1_2: process(all)
570 variable v : reg_stage2_t;
571 variable j : integer;
572 variable k : unsigned(2 downto 0);
573 variable kk : unsigned(3 downto 0);
574 variable idx : unsigned(2 downto 0);
575 variable byte_offset : unsigned(2 downto 0);
579 -- Byte reversing and rotating for stores.
580 -- Done in the second cycle (the cycle after l_in.valid = 1).
581 byte_offset := unsigned(r1.req.addr0(2 downto 0));
583 k := (to_unsigned(i, 3) - byte_offset) xor r1.req.brev_mask;
584 j := to_integer(k) * 8;
585 store_data(i * 8 + 7 downto i * 8) <= r1.req.store_data(j + 7 downto j);
588 if stage3_busy_next = '0' and
589 (r1.req.valid = '0' or r1.issued = '1' or r1.req.dc_req = '0') then
591 v.req.store_data := store_data;
592 v.wait_dc := r1.req.valid and r1.req.dc_req and not r1.req.load_sp and
593 not (r1.req.two_dwords and not r1.req.dword_index);
594 v.wait_mmu := r1.req.valid and r1.req.mmu_op;
595 v.one_cycle := r1.req.valid and (r1.req.noop or r1.req.read_spr or
596 (r1.req.write_spr and not r1.req.mmu_op) or
597 r1.req.load_zero or r1.req.do_update);
598 if r1.req.read_spr = '1' then
600 elsif r1.req.do_update = '1' or r1.req.store = '1' then
602 elsif r1.req.load_sp = '1' then
608 -- Work out load formatter controls for next cycle
610 idx := to_unsigned(i, 3) xor r1.req.brev_mask;
611 kk := ('0' & idx) + ('0' & byte_offset);
612 v.use_second(i) := kk(3);
613 v.byte_index(i) := kk(2 downto 0);
615 elsif stage3_busy_next = '0' then
621 stage2_busy_next <= r1.req.valid and stage3_busy_next;
623 if r3in.interrupt = '1' then
630 -- Processing done in the third cycle of a load/store instruction.
631 -- At this stage we can do things that have side effects without
632 -- fear of the instruction getting flushed. This is the point at
633 -- which requests get sent to the MMU.
634 loadstore1_3: process(all)
635 variable v : reg_stage3_t;
636 variable j : integer;
637 variable req : std_ulogic;
638 variable mmureq : std_ulogic;
639 variable mmu_mtspr : std_ulogic;
640 variable write_enable : std_ulogic;
641 variable write_data : std_ulogic_vector(63 downto 0);
642 variable do_update : std_ulogic;
643 variable done : std_ulogic;
644 variable part_done : std_ulogic;
645 variable exception : std_ulogic;
646 variable data_permuted : std_ulogic_vector(63 downto 0);
647 variable data_trimmed : std_ulogic_vector(63 downto 0);
648 variable sprval : std_ulogic_vector(63 downto 0);
649 variable negative : std_ulogic;
650 variable dsisr : std_ulogic_vector(31 downto 0);
651 variable itlb_fault : std_ulogic;
652 variable trim_ctl : trim_ctl_t;
662 dsisr := (others => '0');
664 sprval := (others => '0');
666 v.convert_lfs := '0';
667 v.srr1 := (others => '0');
669 -- load data formatting
670 -- shift and byte-reverse data bytes
672 j := to_integer(r2.byte_index(i)) * 8;
673 data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
676 -- Work out the sign bit for sign extension.
677 -- For unaligned loads crossing two dwords, the sign bit is in the
678 -- first dword for big-endian (byte_reverse = 1), or the second dword
679 -- for little-endian.
680 if r2.req.dword_index = '1' and r2.req.byte_reverse = '1' then
681 negative := (r2.req.length(3) and r3.load_data(63)) or
682 (r2.req.length(2) and r3.load_data(31)) or
683 (r2.req.length(1) and r3.load_data(15)) or
684 (r2.req.length(0) and r3.load_data(7));
686 negative := (r2.req.length(3) and data_permuted(63)) or
687 (r2.req.length(2) and data_permuted(31)) or
688 (r2.req.length(1) and data_permuted(15)) or
689 (r2.req.length(0) and data_permuted(7));
692 -- trim and sign-extend
694 if i < to_integer(unsigned(r2.req.length)) then
695 if r2.req.dword_index = '1' then
696 trim_ctl(i) := '1' & not r2.use_second(i);
708 data_trimmed(i * 8 + 7 downto i * 8) := r3.load_data(i * 8 + 7 downto i * 8);
710 data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
712 data_trimmed(i * 8 + 7 downto i * 8) := (others => negative and r2.req.sign_extend);
717 -- Single-precision FP conversion for loads
718 v.ld_sp_data := data_trimmed(31 downto 0);
719 v.ld_sp_nz := or (data_trimmed(22 downto 0));
720 v.ld_sp_lz := count_left_zeroes(data_trimmed(22 downto 0));
723 if d_in.valid = '1' and r2.req.load = '1' then
724 v.load_data := data_permuted;
727 if r2.req.valid = '1' then
728 if r2.req.read_spr = '1' then
730 -- partial decode on SPR number should be adequate given
731 -- the restricted set that get sent down this path
732 if r2.req.sprn(9) = '0' and r2.req.sprn(5) = '0' then
733 if r2.req.sprn(0) = '0' then
734 sprval := x"00000000" & r3.dsisr;
739 -- reading one of the SPRs in the MMU
740 sprval := m_in.sprval;
743 if r2.req.align_intr = '1' then
744 -- generate alignment interrupt
747 if r2.req.load_zero = '1' then
750 if r2.req.do_update = '1' then
757 if d_in.valid = '1' then
758 if r2.req.two_dwords = '0' or r2.req.dword_index = '1' then
759 write_enable := r2.req.load and not r2.req.load_sp;
760 if HAS_FPU and r2.req.load_sp = '1' then
761 -- SP to DP conversion takes a cycle
762 v.state := FINISH_LFS;
763 v.convert_lfs := '1';
765 -- stores write back rA update
766 do_update := r2.req.update and r2.req.store;
772 if d_in.error = '1' then
773 if d_in.cache_paradox = '1' then
774 -- signal an interrupt straight away
776 dsisr(63 - 38) := not r2.req.load;
777 -- XXX there is no architected bit for this
778 -- (probably should be a machine check in fact)
779 dsisr(63 - 35) := d_in.cache_paradox;
781 -- Look up the translation for TLB miss
782 -- and also for permission error and RC error
783 -- in case the PTE has been updated.
785 v.state := MMU_LOOKUP;
789 if r2.req.valid = '1' then
790 if r2.req.mmu_op = '1' then
791 -- send request (tlbie, mtspr, itlb miss) to MMU
792 mmureq := not r2.req.write_spr;
793 mmu_mtspr := r2.req.write_spr;
794 if r2.req.instr_fault = '1' then
795 v.state := MMU_LOOKUP;
797 v.state := TLBIE_WAIT;
799 elsif r2.req.write_spr = '1' then
800 if r2.req.sprn(0) = '0' then
801 v.dsisr := r2.req.store_data(31 downto 0);
803 v.dar := r2.req.store_data;
809 if m_in.done = '1' then
810 if r2.req.instr_fault = '0' then
811 -- retry the request now that the MMU has installed a TLB entry
817 if m_in.err = '1' then
819 dsisr(63 - 33) := m_in.invalid;
820 dsisr(63 - 36) := m_in.perm_error;
821 dsisr(63 - 38) := r2.req.store or r2.req.dcbz;
822 dsisr(63 - 44) := m_in.badtree;
823 dsisr(63 - 45) := m_in.rc_error;
833 if complete = '1' or exception = '1' then
838 -- generate DSI or DSegI for load/store exceptions
839 -- or ISI or ISegI for instruction fetch exceptions
840 v.interrupt := exception;
841 if exception = '1' then
843 if r2.req.align_intr = '1' then
844 v.intr_vec := 16#600#;
845 v.dar := r2.req.addr;
846 elsif r2.req.instr_fault = '0' then
847 v.dar := r2.req.addr;
848 if m_in.segerr = '0' then
849 v.intr_vec := 16#300#;
852 v.intr_vec := 16#380#;
855 if m_in.segerr = '0' then
856 v.srr1(47 - 33) := m_in.invalid;
857 v.srr1(47 - 35) := m_in.perm_error; -- noexec fault
858 v.srr1(47 - 44) := m_in.badtree;
859 v.srr1(47 - 45) := m_in.rc_error;
860 v.intr_vec := 16#400#;
862 v.intr_vec := 16#480#;
870 write_data := sprval;
873 write_data := r2.req.addr0;
876 write_data := load_dp_data;
879 write_data := data_trimmed;
882 -- Update outputs to dcache
883 if stage1_issue_enable = '1' then
884 d_out.valid <= stage1_dcreq;
885 d_out.load <= stage1_req.load;
886 d_out.dcbz <= stage1_req.dcbz;
887 d_out.nc <= stage1_req.nc;
888 d_out.reserve <= stage1_req.reserve;
889 d_out.atomic <= stage1_req.atomic;
890 d_out.atomic_last <= stage1_req.atomic_last;
891 d_out.addr <= stage1_req.addr;
892 d_out.byte_sel <= stage1_req.byte_sel;
893 d_out.virt_mode <= stage1_req.virt_mode;
894 d_out.priv_mode <= stage1_req.priv_mode;
897 d_out.load <= r2.req.load;
898 d_out.dcbz <= r2.req.dcbz;
899 d_out.nc <= r2.req.nc;
900 d_out.reserve <= r2.req.reserve;
901 d_out.atomic <= r2.req.atomic;
902 d_out.atomic_last <= r2.req.atomic_last;
903 d_out.addr <= r2.req.addr;
904 d_out.byte_sel <= r2.req.byte_sel;
905 d_out.virt_mode <= r2.req.virt_mode;
906 d_out.priv_mode <= r2.req.priv_mode;
908 if stage1_dreq = '1' then
909 d_out.data <= store_data;
911 d_out.data <= r2.req.store_data;
913 d_out.hold <= r2.req.valid and r2.req.load_sp and d_in.valid;
915 -- Update outputs to MMU
916 m_out.valid <= mmureq;
917 m_out.iside <= r2.req.instr_fault;
918 m_out.load <= r2.req.load;
919 m_out.priv <= r2.req.priv_mode;
920 m_out.tlbie <= r2.req.tlbie;
921 m_out.mtspr <= mmu_mtspr;
922 m_out.sprn <= r2.req.sprn;
923 m_out.addr <= r2.req.addr;
924 m_out.slbia <= r2.req.is_slbia;
925 m_out.rs <= r2.req.store_data;
927 -- Update outputs to writeback
928 l_out.valid <= complete;
929 l_out.instr_tag <= r2.req.instr_tag;
930 l_out.write_enable <= write_enable or do_update;
931 l_out.write_reg <= r2.req.write_reg;
932 l_out.write_data <= write_data;
933 l_out.xerc <= r2.req.xerc;
934 l_out.rc <= r2.req.rc and complete;
935 l_out.store_done <= d_in.store_done;
936 l_out.interrupt <= r3.interrupt;
937 l_out.intr_vec <= r3.intr_vec;
938 l_out.srr0 <= r3.nia;
939 l_out.srr1 <= r3.srr1;
941 -- update busy signal back to execute1
945 stage3_busy_next <= r2.req.valid and not (complete or part_done or exception);
952 l1_log: if LOG_LENGTH > 0 generate
953 signal log_data : std_ulogic_vector(9 downto 0);
955 ls1_log: process(clk)
957 if rising_edge(clk) then
958 log_data <= e_out.busy &
965 std_ulogic_vector(to_unsigned(state_t'pos(r3.state), 3));