2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.decode_types.all;
8 use work.insn_helpers.all;
12 -- We calculate the address in the first cycle
16 HAS_FPU : boolean := true;
17 -- Non-zero to enable log data collection
18 LOG_LENGTH : natural := 0
24 l_in : in Execute1ToLoadstore1Type;
25 e_out : out Loadstore1ToExecute1Type;
26 l_out : out Loadstore1ToWritebackType;
28 d_out : out Loadstore1ToDcacheType;
29 d_in : in DcacheToLoadstore1Type;
31 m_out : out Loadstore1ToMmuType;
32 m_in : in MmuToLoadstore1Type;
34 dc_stall : in std_ulogic;
36 log_out : out std_ulogic_vector(9 downto 0)
40 architecture behave of loadstore1 is
42 -- State machine for unaligned loads/stores
43 type state_t is (IDLE, -- ready for instruction
44 MMU_LOOKUP, -- waiting for MMU to look up translation
45 TLBIE_WAIT, -- waiting for MMU to finish doing a tlbie
46 FINISH_LFS -- write back converted SP data for lfs*
49 type byte_index_t is array(0 to 7) of unsigned(2 downto 0);
50 subtype byte_trim_t is std_ulogic_vector(1 downto 0);
51 type trim_ctl_t is array(0 to 7) of byte_trim_t;
53 type request_t is record
60 read_spr : std_ulogic;
61 write_spr : std_ulogic;
63 instr_fault : std_ulogic;
64 load_zero : std_ulogic;
65 do_update : std_ulogic;
67 mode_32bit : std_ulogic;
68 addr : std_ulogic_vector(63 downto 0);
69 addr0 : std_ulogic_vector(63 downto 0);
70 byte_sel : std_ulogic_vector(7 downto 0);
71 second_bytes : std_ulogic_vector(7 downto 0);
72 store_data : std_ulogic_vector(63 downto 0);
73 instr_tag : instr_tag_t;
74 write_reg : gspr_index_t;
75 length : std_ulogic_vector(3 downto 0);
76 elt_length : std_ulogic_vector(3 downto 0);
77 byte_reverse : std_ulogic;
78 brev_mask : unsigned(2 downto 0);
79 sign_extend : std_ulogic;
84 atomic_last : std_ulogic;
86 nc : std_ulogic; -- non-cacheable access
87 virt_mode : std_ulogic;
88 priv_mode : std_ulogic;
90 sprn : std_ulogic_vector(9 downto 0);
91 is_slbia : std_ulogic;
92 align_intr : std_ulogic;
93 dword_index : std_ulogic;
94 two_dwords : std_ulogic;
95 nia : std_ulogic_vector(63 downto 0);
97 constant request_init : request_t := (valid => '0', dc_req => '0', load => '0', store => '0', tlbie => '0',
98 dcbz => '0', read_spr => '0', write_spr => '0', mmu_op => '0',
99 instr_fault => '0', load_zero => '0', do_update => '0', noop => '0',
100 mode_32bit => '0', addr => (others => '0'), addr0 => (others => '0'),
101 byte_sel => x"00", second_bytes => x"00",
102 store_data => (others => '0'), instr_tag => instr_tag_init,
103 write_reg => 7x"00", length => x"0",
104 elt_length => x"0", byte_reverse => '0', brev_mask => "000",
105 sign_extend => '0', update => '0',
106 xerc => xerc_init, reserve => '0',
107 atomic => '0', atomic_last => '0', rc => '0', nc => '0',
108 virt_mode => '0', priv_mode => '0', load_sp => '0',
109 sprn => 10x"0", is_slbia => '0', align_intr => '0',
110 dword_index => '0', two_dwords => '0',
111 nia => (others => '0'));
113 type reg_stage1_t is record
118 type reg_stage2_t is record
120 byte_index : byte_index_t;
121 use_second : std_ulogic_vector(7 downto 0);
122 wait_dc : std_ulogic;
123 wait_mmu : std_ulogic;
124 one_cycle : std_ulogic;
125 wr_sel : std_ulogic_vector(1 downto 0);
128 type reg_stage3_t is record
130 instr_tag : instr_tag_t;
131 write_enable : std_ulogic;
132 write_reg : gspr_index_t;
133 write_data : std_ulogic_vector(63 downto 0);
136 store_done : std_ulogic;
137 convert_lfs : std_ulogic;
138 load_data : std_ulogic_vector(63 downto 0);
139 dar : std_ulogic_vector(63 downto 0);
140 dsisr : std_ulogic_vector(31 downto 0);
141 ld_sp_data : std_ulogic_vector(31 downto 0);
142 ld_sp_nz : std_ulogic;
143 ld_sp_lz : std_ulogic_vector(5 downto 0);
144 stage1_en : std_ulogic;
145 interrupt : std_ulogic;
146 intr_vec : integer range 0 to 16#fff#;
147 nia : std_ulogic_vector(63 downto 0);
148 srr1 : std_ulogic_vector(15 downto 0);
151 signal req_in : request_t;
152 signal r1, r1in : reg_stage1_t;
153 signal r2, r2in : reg_stage2_t;
154 signal r3, r3in : reg_stage3_t;
156 signal busy : std_ulogic;
157 signal complete : std_ulogic;
158 signal in_progress : std_ulogic;
159 signal flushing : std_ulogic;
161 signal store_sp_data : std_ulogic_vector(31 downto 0);
162 signal load_dp_data : std_ulogic_vector(63 downto 0);
163 signal store_data : std_ulogic_vector(63 downto 0);
165 signal stage1_issue_enable : std_ulogic;
166 signal stage1_req : request_t;
167 signal stage1_dcreq : std_ulogic;
168 signal stage1_dreq : std_ulogic;
169 signal stage2_busy_next : std_ulogic;
170 signal stage3_busy_next : std_ulogic;
172 -- Generate byte enables from sizes
173 function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
187 end function length_to_sel;
189 -- Calculate byte enables
190 -- This returns 16 bits, giving the select signals for two transfers,
191 -- to account for unaligned loads or stores
192 function xfer_data_sel(size : in std_logic_vector(3 downto 0);
193 address : in std_logic_vector(2 downto 0))
194 return std_ulogic_vector is
195 variable longsel : std_ulogic_vector(15 downto 0);
197 longsel := "00000000" & length_to_sel(size);
198 return std_ulogic_vector(shift_left(unsigned(longsel),
199 to_integer(unsigned(address))));
200 end function xfer_data_sel;
202 -- 23-bit right shifter for DP -> SP float conversions
203 function shifter_23r(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
204 return std_ulogic_vector is
205 variable fs1 : std_ulogic_vector(22 downto 0);
206 variable fs2 : std_ulogic_vector(22 downto 0);
208 case shift(1 downto 0) is
212 fs1 := '0' & frac(22 downto 1);
214 fs1 := "00" & frac(22 downto 2);
216 fs1 := "000" & frac(22 downto 3);
218 case shift(4 downto 2) is
222 fs2 := x"0" & fs1(22 downto 4);
224 fs2 := x"00" & fs1(22 downto 8);
226 fs2 := x"000" & fs1(22 downto 12);
228 fs2 := x"0000" & fs1(22 downto 16);
230 fs2 := x"00000" & fs1(22 downto 20);
235 -- 23-bit left shifter for SP -> DP float conversions
236 function shifter_23l(frac: std_ulogic_vector(22 downto 0); shift: unsigned(4 downto 0))
237 return std_ulogic_vector is
238 variable fs1 : std_ulogic_vector(22 downto 0);
239 variable fs2 : std_ulogic_vector(22 downto 0);
241 case shift(1 downto 0) is
245 fs1 := frac(21 downto 0) & '0';
247 fs1 := frac(20 downto 0) & "00";
249 fs1 := frac(19 downto 0) & "000";
251 case shift(4 downto 2) is
255 fs2 := fs1(18 downto 0) & x"0" ;
257 fs2 := fs1(14 downto 0) & x"00";
259 fs2 := fs1(10 downto 0) & x"000";
261 fs2 := fs1(6 downto 0) & x"0000";
263 fs2 := fs1(2 downto 0) & x"00000";
269 loadstore1_reg: process(clk)
271 if rising_edge(clk) then
279 r3.write_enable <= '0';
282 r3.convert_lfs <= '0';
288 flushing <= (flushing or (r1in.req.valid and r1in.req.align_intr)) and
291 stage1_dreq <= stage1_dcreq;
292 if d_in.valid = '1' then
293 assert r2.req.valid = '1' and r2.req.dc_req = '1' and r3.state = IDLE severity failure;
295 if d_in.error = '1' then
296 assert r2.req.valid = '1' and r2.req.dc_req = '1' and r3.state = IDLE severity failure;
298 if m_in.done = '1' or m_in.err = '1' then
299 assert r2.req.valid = '1' and (r3.state = MMU_LOOKUP or r3.state = TLBIE_WAIT) severity failure;
304 ls_fp_conv: if HAS_FPU generate
305 -- Convert DP data to SP for stfs
306 dp_to_sp: process(all)
307 variable exp : unsigned(10 downto 0);
308 variable frac : std_ulogic_vector(22 downto 0);
309 variable shift : unsigned(4 downto 0);
311 store_sp_data(31) <= l_in.data(63);
312 store_sp_data(30 downto 0) <= (others => '0');
313 exp := unsigned(l_in.data(62 downto 52));
315 store_sp_data(30) <= l_in.data(62);
316 store_sp_data(29 downto 0) <= l_in.data(58 downto 29);
317 elsif exp >= 874 then
318 -- denormalization required
319 frac := '1' & l_in.data(51 downto 30);
320 shift := 0 - exp(4 downto 0);
321 store_sp_data(22 downto 0) <= shifter_23r(frac, shift);
325 -- Convert SP data to DP for lfs
326 sp_to_dp: process(all)
327 variable exp : unsigned(7 downto 0);
328 variable exp_dp : unsigned(10 downto 0);
329 variable exp_nz : std_ulogic;
330 variable exp_ao : std_ulogic;
331 variable frac : std_ulogic_vector(22 downto 0);
332 variable frac_shift : unsigned(4 downto 0);
334 frac := r3.ld_sp_data(22 downto 0);
335 exp := unsigned(r3.ld_sp_data(30 downto 23));
336 exp_nz := or (r3.ld_sp_data(30 downto 23));
337 exp_ao := and (r3.ld_sp_data(30 downto 23));
338 frac_shift := (others => '0');
340 exp_dp := to_unsigned(2047, 11); -- infinity or NaN
341 elsif exp_nz = '1' then
342 exp_dp := 896 + resize(exp, 11); -- finite normalized value
343 elsif r3.ld_sp_nz = '0' then
344 exp_dp := to_unsigned(0, 11); -- zero
346 -- denormalized SP operand, need to normalize
347 exp_dp := 896 - resize(unsigned(r3.ld_sp_lz), 11);
348 frac_shift := unsigned(r3.ld_sp_lz(4 downto 0)) + 1;
350 load_dp_data(63) <= r3.ld_sp_data(31);
351 load_dp_data(62 downto 52) <= std_ulogic_vector(exp_dp);
352 load_dp_data(51 downto 29) <= shifter_23l(frac, frac_shift);
353 load_dp_data(28 downto 0) <= (others => '0');
357 -- Translate a load/store instruction into the internal request format
358 -- XXX this should only depend on l_in, but actually depends on
359 -- r1.req.addr0 as well (in the l_in.second = 1 case).
360 loadstore1_in: process(all)
361 variable v : request_t;
362 variable lsu_sum : std_ulogic_vector(63 downto 0);
363 variable brev_lenm1 : unsigned(2 downto 0);
364 variable long_sel : std_ulogic_vector(15 downto 0);
365 variable addr : std_ulogic_vector(63 downto 0);
366 variable sprn : std_ulogic_vector(9 downto 0);
367 variable misaligned : std_ulogic;
368 variable addr_mask : std_ulogic_vector(2 downto 0);
371 sprn := std_ulogic_vector(to_unsigned(decode_spr_num(l_in.insn), 10));
373 v.valid := l_in.valid;
374 v.instr_tag := l_in.instr_tag;
375 v.mode_32bit := l_in.mode_32bit;
376 v.write_reg := l_in.write_reg;
377 v.length := l_in.length;
378 v.elt_length := l_in.length;
379 v.byte_reverse := l_in.byte_reverse;
380 v.sign_extend := l_in.sign_extend;
381 v.update := l_in.update;
383 v.reserve := l_in.reserve;
386 v.virt_mode := l_in.virt_mode;
387 v.priv_mode := l_in.priv_mode;
391 lsu_sum := std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2));
393 if HAS_FPU and l_in.is_32bit = '1' then
394 v.store_data := x"00000000" & store_sp_data;
396 v.store_data := l_in.data;
401 if l_in.second = '1' then
402 if l_in.update = '0' then
403 -- for the second half of a 16-byte transfer,
404 -- use the previous address plus 8.
405 addr := std_ulogic_vector(unsigned(r1.req.addr0(63 downto 3)) + 1) & r1.req.addr0(2 downto 0);
407 -- for an update-form load, use the previous address
408 -- as the value to write back to RA.
409 addr := r1.req.addr0;
412 if l_in.mode_32bit = '1' then
413 addr(63 downto 32) := (others => '0');
418 -- XXX Temporary hack. Mark the op as non-cachable if the address
419 -- is the form 0xc------- for a real-mode access.
420 if addr(31 downto 28) = "1100" and l_in.virt_mode = '0' then
424 addr_mask := std_ulogic_vector(unsigned(l_in.length(2 downto 0)) - 1);
426 -- Do length_to_sel and work out if we are doing 2 dwords
427 long_sel := xfer_data_sel(v.length, addr(2 downto 0));
428 v.byte_sel := long_sel(7 downto 0);
429 v.second_bytes := long_sel(15 downto 8);
430 if long_sel(15 downto 8) /= "00000000" then
434 -- check alignment for larx/stcx
435 misaligned := or (addr_mask and addr(2 downto 0));
436 v.align_intr := l_in.reserve and misaligned;
437 if l_in.repeat = '1' and l_in.second = '0' and l_in.update = '0' and addr(3) = '1' then
438 -- length is really 16 not 8
439 -- Make misaligned lq cause an alignment interrupt in LE mode,
440 -- in order to avoid the case with RA = RT + 1 where the second half
441 -- faults but the first doesn't (and updates RT+1, destroying RA).
442 -- The equivalent BE case doesn't occur because RA = RT is illegal.
444 if l_in.reserve = '1' or (l_in.op = OP_LOAD and l_in.byte_reverse = '0') then
449 v.atomic := not misaligned;
450 v.atomic_last := not misaligned and (l_in.second or not l_in.repeat);
456 if l_in.update = '0' or l_in.second = '0' then
458 if HAS_FPU and l_in.is_32bit = '1' then
459 -- Allow an extra cycle for SP->DP precision conversion
463 -- write back address to RA
468 v.align_intr := v.nc;
471 v.addr := l_in.addr2; -- address from RB for tlbie
472 v.is_slbia := l_in.insn(7);
478 v.mmu_op := sprn(9) or sprn(5);
479 when OP_FETCH_FAILED =>
480 -- send it to the MMU to do the radix walk
481 v.instr_fault := '1';
486 v.dc_req := l_in.valid and (v.load or v.store or v.dcbz) and not v.align_intr;
488 -- Work out controls for load and store formatting
490 if v.byte_reverse = '1' then
491 brev_lenm1 := unsigned(v.length(2 downto 0)) - 1;
493 v.brev_mask := brev_lenm1;
498 busy <= r1.req.valid and ((r1.req.dc_req and not r1.issued) or
499 (r1.issued and d_in.error) or
501 (r1.req.dc_req and r1.req.two_dwords and not r1.req.dword_index));
502 complete <= r2.one_cycle or (r2.wait_dc and d_in.valid) or
503 (r2.wait_mmu and m_in.done) or r3.convert_lfs;
504 in_progress <= r1.req.valid or (r2.req.valid and not complete);
506 stage1_issue_enable <= r3.stage1_en and not (r1.req.valid and r1.req.mmu_op) and
507 not (r2.req.valid and r2.req.mmu_op);
509 -- Processing done in the first cycle of a load/store instruction
510 loadstore1_1: process(all)
511 variable v : reg_stage1_t;
512 variable req : request_t;
513 variable dcreq : std_ulogic;
514 variable addr : std_ulogic_vector(63 downto 0);
519 if flushing = '1' then
520 -- Make this a no-op request rather than simply invalid.
521 -- It will never get to stage 3 since there is a request ahead of
522 -- it with align_intr = 1.
526 -- Note that l_in.valid is gated with busy inside execute1
527 if l_in.valid = '1' then
528 dcreq := req.dc_req and stage1_issue_enable and not d_in.error and not dc_stall;
531 elsif r1.req.valid = '1' then
532 if r1.req.dc_req = '1' and r1.issued = '0' then
534 dcreq := stage1_issue_enable and not dc_stall and not d_in.error;
536 elsif r1.issued = '1' and d_in.error = '1' then
538 elsif stage2_busy_next = '0' then
539 -- we can change what's in r1 next cycle because the current thing
540 -- in r1 will go into r2
541 if r1.req.dc_req = '1' and r1.req.two_dwords = '1' and r1.req.dword_index = '0' then
542 -- construct the second request for a misaligned access
543 v.req.dword_index := '1';
544 v.req.addr := std_ulogic_vector(unsigned(r1.req.addr(63 downto 3)) + 1) & "000";
545 if r1.req.mode_32bit = '1' then
546 v.req.addr(32) := '0';
548 v.req.byte_sel := r1.req.second_bytes;
549 v.issued := stage1_issue_enable and not dc_stall;
550 dcreq := stage1_issue_enable and not dc_stall;
557 if r3in.interrupt = '1' then
563 stage1_dcreq <= dcreq;
567 -- Processing done in the second cycle of a load/store instruction.
568 -- Store data is formatted here and sent to the dcache.
569 -- The request in r1 is sent to stage 3 if stage 3 will not be busy next cycle.
570 loadstore1_2: process(all)
571 variable v : reg_stage2_t;
572 variable j : integer;
573 variable k : unsigned(2 downto 0);
574 variable kk : unsigned(3 downto 0);
575 variable idx : unsigned(2 downto 0);
576 variable byte_offset : unsigned(2 downto 0);
580 -- Byte reversing and rotating for stores.
581 -- Done in the second cycle (the cycle after l_in.valid = 1).
582 byte_offset := unsigned(r1.req.addr0(2 downto 0));
584 k := (to_unsigned(i, 3) - byte_offset) xor r1.req.brev_mask;
585 j := to_integer(k) * 8;
586 store_data(i * 8 + 7 downto i * 8) <= r1.req.store_data(j + 7 downto j);
589 if stage3_busy_next = '0' and
590 (r1.req.valid = '0' or r1.issued = '1' or r1.req.dc_req = '0') then
592 v.req.store_data := store_data;
593 v.wait_dc := r1.req.valid and r1.req.dc_req and not r1.req.load_sp and
594 not (r1.req.two_dwords and not r1.req.dword_index);
595 v.wait_mmu := r1.req.valid and r1.req.mmu_op;
596 v.one_cycle := r1.req.valid and (r1.req.noop or r1.req.read_spr or
597 (r1.req.write_spr and not r1.req.mmu_op) or
598 r1.req.load_zero or r1.req.do_update);
599 if r1.req.read_spr = '1' then
601 elsif r1.req.do_update = '1' or r1.req.store = '1' then
603 elsif r1.req.load_sp = '1' then
609 -- Work out load formatter controls for next cycle
611 idx := to_unsigned(i, 3) xor r1.req.brev_mask;
612 kk := ('0' & idx) + ('0' & byte_offset);
613 v.use_second(i) := kk(3);
614 v.byte_index(i) := kk(2 downto 0);
616 elsif stage3_busy_next = '0' then
622 stage2_busy_next <= r1.req.valid and stage3_busy_next;
624 if r3in.interrupt = '1' then
631 -- Processing done in the third cycle of a load/store instruction.
632 -- At this stage we can do things that have side effects without
633 -- fear of the instruction getting flushed. This is the point at
634 -- which requests get sent to the MMU.
635 loadstore1_3: process(all)
636 variable v : reg_stage3_t;
637 variable j : integer;
638 variable req : std_ulogic;
639 variable mmureq : std_ulogic;
640 variable mmu_mtspr : std_ulogic;
641 variable write_enable : std_ulogic;
642 variable write_data : std_ulogic_vector(63 downto 0);
643 variable do_update : std_ulogic;
644 variable done : std_ulogic;
645 variable part_done : std_ulogic;
646 variable exception : std_ulogic;
647 variable data_permuted : std_ulogic_vector(63 downto 0);
648 variable data_trimmed : std_ulogic_vector(63 downto 0);
649 variable sprval : std_ulogic_vector(63 downto 0);
650 variable negative : std_ulogic;
651 variable dsisr : std_ulogic_vector(31 downto 0);
652 variable itlb_fault : std_ulogic;
653 variable trim_ctl : trim_ctl_t;
663 dsisr := (others => '0');
665 sprval := (others => '0');
667 v.convert_lfs := '0';
668 v.srr1 := (others => '0');
670 -- load data formatting
671 -- shift and byte-reverse data bytes
673 j := to_integer(r2.byte_index(i)) * 8;
674 data_permuted(i * 8 + 7 downto i * 8) := d_in.data(j + 7 downto j);
677 -- Work out the sign bit for sign extension.
678 -- For unaligned loads crossing two dwords, the sign bit is in the
679 -- first dword for big-endian (byte_reverse = 1), or the second dword
680 -- for little-endian.
681 if r2.req.dword_index = '1' and r2.req.byte_reverse = '1' then
682 negative := (r2.req.length(3) and r3.load_data(63)) or
683 (r2.req.length(2) and r3.load_data(31)) or
684 (r2.req.length(1) and r3.load_data(15)) or
685 (r2.req.length(0) and r3.load_data(7));
687 negative := (r2.req.length(3) and data_permuted(63)) or
688 (r2.req.length(2) and data_permuted(31)) or
689 (r2.req.length(1) and data_permuted(15)) or
690 (r2.req.length(0) and data_permuted(7));
693 -- trim and sign-extend
695 if i < to_integer(unsigned(r2.req.length)) then
696 if r2.req.dword_index = '1' then
697 trim_ctl(i) := '1' & not r2.use_second(i);
709 data_trimmed(i * 8 + 7 downto i * 8) := r3.load_data(i * 8 + 7 downto i * 8);
711 data_trimmed(i * 8 + 7 downto i * 8) := data_permuted(i * 8 + 7 downto i * 8);
713 data_trimmed(i * 8 + 7 downto i * 8) := (others => negative and r2.req.sign_extend);
718 -- Single-precision FP conversion for loads
719 v.ld_sp_data := data_trimmed(31 downto 0);
720 v.ld_sp_nz := or (data_trimmed(22 downto 0));
721 v.ld_sp_lz := count_left_zeroes(data_trimmed(22 downto 0));
724 if d_in.valid = '1' and r2.req.load = '1' then
725 v.load_data := data_permuted;
728 if r2.req.valid = '1' then
729 if r2.req.read_spr = '1' then
731 -- partial decode on SPR number should be adequate given
732 -- the restricted set that get sent down this path
733 if r2.req.sprn(9) = '0' and r2.req.sprn(5) = '0' then
734 if r2.req.sprn(0) = '0' then
735 sprval := x"00000000" & r3.dsisr;
740 -- reading one of the SPRs in the MMU
741 sprval := m_in.sprval;
744 if r2.req.align_intr = '1' then
745 -- generate alignment interrupt
748 if r2.req.load_zero = '1' then
751 if r2.req.do_update = '1' then
758 if d_in.valid = '1' then
759 if r2.req.two_dwords = '0' or r2.req.dword_index = '1' then
760 write_enable := r2.req.load and not r2.req.load_sp;
761 if HAS_FPU and r2.req.load_sp = '1' then
762 -- SP to DP conversion takes a cycle
763 v.state := FINISH_LFS;
764 v.convert_lfs := '1';
766 -- stores write back rA update
767 do_update := r2.req.update and r2.req.store;
773 if d_in.error = '1' then
774 if d_in.cache_paradox = '1' then
775 -- signal an interrupt straight away
777 dsisr(63 - 38) := not r2.req.load;
778 -- XXX there is no architected bit for this
779 -- (probably should be a machine check in fact)
780 dsisr(63 - 35) := d_in.cache_paradox;
782 -- Look up the translation for TLB miss
783 -- and also for permission error and RC error
784 -- in case the PTE has been updated.
786 v.state := MMU_LOOKUP;
790 if r2.req.valid = '1' then
791 if r2.req.mmu_op = '1' then
792 -- send request (tlbie, mtspr, itlb miss) to MMU
793 mmureq := not r2.req.write_spr;
794 mmu_mtspr := r2.req.write_spr;
795 if r2.req.instr_fault = '1' then
796 v.state := MMU_LOOKUP;
798 v.state := TLBIE_WAIT;
800 elsif r2.req.write_spr = '1' then
801 if r2.req.sprn(0) = '0' then
802 v.dsisr := r2.req.store_data(31 downto 0);
804 v.dar := r2.req.store_data;
810 if m_in.done = '1' then
811 if r2.req.instr_fault = '0' then
812 -- retry the request now that the MMU has installed a TLB entry
818 if m_in.err = '1' then
820 dsisr(63 - 33) := m_in.invalid;
821 dsisr(63 - 36) := m_in.perm_error;
822 dsisr(63 - 38) := r2.req.store or r2.req.dcbz;
823 dsisr(63 - 44) := m_in.badtree;
824 dsisr(63 - 45) := m_in.rc_error;
834 if complete = '1' or exception = '1' then
839 -- generate DSI or DSegI for load/store exceptions
840 -- or ISI or ISegI for instruction fetch exceptions
841 v.interrupt := exception;
842 if exception = '1' then
844 if r2.req.align_intr = '1' then
845 v.intr_vec := 16#600#;
846 v.dar := r2.req.addr;
847 elsif r2.req.instr_fault = '0' then
848 v.dar := r2.req.addr;
849 if m_in.segerr = '0' then
850 v.intr_vec := 16#300#;
853 v.intr_vec := 16#380#;
856 if m_in.segerr = '0' then
857 v.srr1(47 - 33) := m_in.invalid;
858 v.srr1(47 - 35) := m_in.perm_error; -- noexec fault
859 v.srr1(47 - 44) := m_in.badtree;
860 v.srr1(47 - 45) := m_in.rc_error;
861 v.intr_vec := 16#400#;
863 v.intr_vec := 16#480#;
871 write_data := sprval;
874 write_data := r2.req.addr0;
877 write_data := load_dp_data;
880 write_data := data_trimmed;
883 -- Update outputs to dcache
884 if stage1_issue_enable = '1' then
885 d_out.valid <= stage1_dcreq;
886 d_out.load <= stage1_req.load;
887 d_out.dcbz <= stage1_req.dcbz;
888 d_out.nc <= stage1_req.nc;
889 d_out.reserve <= stage1_req.reserve;
890 d_out.atomic <= stage1_req.atomic;
891 d_out.atomic_last <= stage1_req.atomic_last;
892 d_out.addr <= stage1_req.addr;
893 d_out.byte_sel <= stage1_req.byte_sel;
894 d_out.virt_mode <= stage1_req.virt_mode;
895 d_out.priv_mode <= stage1_req.priv_mode;
898 d_out.load <= r2.req.load;
899 d_out.dcbz <= r2.req.dcbz;
900 d_out.nc <= r2.req.nc;
901 d_out.reserve <= r2.req.reserve;
902 d_out.atomic <= r2.req.atomic;
903 d_out.atomic_last <= r2.req.atomic_last;
904 d_out.addr <= r2.req.addr;
905 d_out.byte_sel <= r2.req.byte_sel;
906 d_out.virt_mode <= r2.req.virt_mode;
907 d_out.priv_mode <= r2.req.priv_mode;
909 if stage1_dreq = '1' then
910 d_out.data <= store_data;
912 d_out.data <= r2.req.store_data;
914 d_out.hold <= r2.req.valid and r2.req.load_sp and d_in.valid;
916 -- Update outputs to MMU
917 m_out.valid <= mmureq;
918 m_out.iside <= r2.req.instr_fault;
919 m_out.load <= r2.req.load;
920 m_out.priv <= r2.req.priv_mode;
921 m_out.tlbie <= r2.req.tlbie;
922 m_out.mtspr <= mmu_mtspr;
923 m_out.sprn <= r2.req.sprn;
924 m_out.addr <= r2.req.addr;
925 m_out.slbia <= r2.req.is_slbia;
926 m_out.rs <= r2.req.store_data;
928 -- Update outputs to writeback
929 l_out.valid <= complete;
930 l_out.instr_tag <= r2.req.instr_tag;
931 l_out.write_enable <= write_enable or do_update;
932 l_out.write_reg <= r2.req.write_reg;
933 l_out.write_data <= write_data;
934 l_out.xerc <= r2.req.xerc;
935 l_out.rc <= r2.req.rc and complete;
936 l_out.store_done <= d_in.store_done;
937 l_out.interrupt <= r3.interrupt;
938 l_out.intr_vec <= r3.intr_vec;
939 l_out.srr0 <= r3.nia;
940 l_out.srr1 <= r3.srr1;
942 -- update busy signal back to execute1
944 e_out.in_progress <= in_progress;
947 stage3_busy_next <= r2.req.valid and not (complete or part_done or exception);
954 l1_log: if LOG_LENGTH > 0 generate
955 signal log_data : std_ulogic_vector(9 downto 0);
957 ls1_log: process(clk)
959 if rising_edge(clk) then
960 log_data <= e_out.busy &
967 std_ulogic_vector(to_unsigned(state_t'pos(r3.state), 3));