ls180/experiment9_recon/run_iverilog_ls180.sh

   1 #!/bin/sh
   2
   3 SRCDIR=../../soclayout/experiments9/non_generated/
   4 cp $SRCDIR/full_core_4_4ksram_litex_ls180_recon.v litex_ls180.v
   5 cp $SRCDIR/full_core_4_4ksram_libresoc_recon.v libresoc.v
   6 cp $SRCDIR/pll.v .
   7 cp $SRCDIR/ls180.v .
   8
   9 touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
  10 # Only run test in reset state as running CPU takes too much time to simulate
  11 make \
  12   SIM=icarus \
  13   TOPLEVEL=ls180 \
  14   COCOTB_RESULTS_FILE=results_iverilog_ls180.xml \
  15   COCOTB_HDL_TIMEUNIT=100ps \
  16   TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset" \
  17   SIM_BUILD=sim_build_iverilog_ls180
  18
  19