ls180/pll.v

   1 // PLL simulation model; just connect input clock to output clock
   2 module pll(ref_v, div_out_test, a0, a1, vco_test_ana, out_v);
   3   input a0;
   4   input a1;
   5   output div_out_test;
   6   output out_v;
   7   input ref_v;
   8   output vco_test_ana;
   9
  10 assign out_v = ref_v;
  11 assign vco_test_ana = 0;
  12 assign div_out_test = 0;
  13
  14 endmodule
  15