add ghdl wishbone basic test
[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb / run_ghdl_wb.sh
1 #!/bin/sh
2
3 # Only run test in reset state as running CPU takes too much time to simulate
4 make \
5 SIM=ghdl \
6 COCOTB_RESULTS_FILE=results_iverilog.xml \
7 COCOTB_HDL_TIMEUNIT=100ps \
8 TESTCASE="wishbone_basic" \
9 SIM_BUILD=sim_build_iverilog
10
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