ls180/post_pnr/cocotb/test.py

   1 import cocotb
   2 from cocotb.clock import Clock
   3 from cocotb.triggers import Timer
   4 from cocotb.utils import get_sim_steps
   5 from cocotb.binary import BinaryValue
   6
   7 from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
   8 from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
   9
  10 from itertools import chain
  11
  12 import cocotb
  13 from cocotb.clock import Clock
  14 from cocotb.triggers import Timer
  15 from cocotb.utils import get_sim_steps
  16 from cocotb.binary import BinaryValue
  17
  18 from c4m.nmigen.jtag.tap import IOType
  19 from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
  20 from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
  21
  22 from soc.config.pinouts import get_pinspecs
  23 from soc.debug.jtag import Pins
  24
  25 #
  26 # Helper functions
  27 #
  28
  29 def setup_sim(dut, *, clk_period, run):
  30     """Initialize CPU and setup clock"""
  31
  32     clk_steps = get_sim_steps(clk_period, "ns")
  33     cocotb.fork(Clock(dut.sys_clk, clk_steps).start())
  34
  35     dut.vdd <= 1
  36     dut.vss <= 0
  37     dut.iovdd <= 1
  38     dut.iovss <= 0
  39     dut.sys_rst <= 1
  40     dut.sys_clk <= 0
  41     # adder test (ignore this)
  42     #dut.a <= 3
  43     #dut.b <= 2
  44
  45     if run:
  46         yield Timer(int(10.5*clk_steps))
  47         dut.sys_rst <= 0
  48         yield Timer(int(5*clk_steps))
  49
  50 def setup_jtag(dut, *, tck_period):
  51     # Make this a generator
  52     if False:
  53         yield Timer(0)
  54     clk_steps = get_sim_steps(tck_period, "ns")
  55     return JTAG_Master(dut.jtag_tck, dut.jtag_tms,
  56                        dut.jtag_tdi, dut.jtag_tdo,
  57                        clk_period=clk_steps,
  58                        ir_width=4)
  59
  60 def execute_svf(dut, *, jtag, svf_filename):
  61     jtag_svf = SVF_Executor(jtag)
  62     with open(svf_filename, "r") as f:
  63         svf_deck = f.read()
  64     yield jtag_svf.run(svf_deck, p=dut._log.info)
  65
  66 #
  67 # IDCODE using JTAG_master
  68 #
  69
  70 def idcode(dut, *, jtag):
  71     #jtag.IDCODE = [0, 0, 0, 1]
  72     yield jtag.idcode()
  73     result1 = jtag.result
  74     dut._log.info("IDCODE1: {}".format(result1))
  75     assert(result1 == BinaryValue("00000000000000000001100011111111"))
  76
  77     yield jtag.idcode()
  78     result2 = jtag.result
  79     dut._log.info("IDCODE2: {}".format(result2))
  80
  81     assert(result1 == result2)
  82
  83 @cocotb.test()
  84 def idcode_reset(dut):
  85     dut._log.info("Running IDCODE test; cpu in reset...")
  86
  87     clk_period = 100 # 10MHz
  88     tck_period = 300 # 3MHz
  89
  90     yield from setup_sim(dut, clk_period=clk_period, run=False)
  91     jtag = yield from setup_jtag(dut, tck_period = tck_period)
  92
  93     yield from idcode(dut, jtag=jtag)
  94
  95     dut._log.info("IDCODE test completed")
  96
  97 @cocotb.test()
  98 def idcode_run(dut):
  99     dut._log.info("Running IDCODE test; cpu running...")
 100
 101     clk_period = 100 # 10MHz
 102     tck_period = 300 # 3MHz
 103
 104     yield from setup_sim(dut, clk_period=clk_period, run=True)
 105     jtag = yield from setup_jtag(dut, tck_period = tck_period)
 106
 107     yield from idcode(dut, jtag=jtag)
 108
 109     dut._log.info("IDCODE test completed")
 110
 111 #
 112 # Read IDCODE from SVF file
 113 #
 114
 115 @cocotb.test()
 116 def idcodesvf_reset(dut):
 117     dut._log.info("Running IDCODE through SVF test; cpu in reset...")
 118
 119     clk_period = 100 # 10MHz
 120     tck_period = 300 # 3MHz
 121
 122     yield from setup_sim(dut, clk_period=clk_period, run=False)
 123     jtag = yield from setup_jtag(dut, tck_period = tck_period)
 124
 125     yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
 126
 127     dut._log.info("IDCODE test completed")
 128
 129 @cocotb.test()
 130 def idcode_run_svf(dut):
 131     dut._log.info("Running IDCODE through test; cpu running...")
 132
 133     clk_period = 100 # 10MHz
 134     tck_period = 300 # 3MHz
 135
 136     yield from setup_sim(dut, clk_period=clk_period, run=True)
 137     jtag = yield from setup_jtag(dut, tck_period = tck_period)
 138
 139     yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
 140
 141     dut._log.info("IDCODE test completed")
 142
 143
 144 @cocotb.test()
 145 def wishbone_basic(dut):
 146     """
 147     Test of an added Wishbone interface
 148     """
 149     clk_period = 100 # 100MHz
 150     tck_period = 3000 # 0.3MHz
 151
 152     data_in = BinaryValue()
 153     # these have to match with soc.debug.jtag.JTAG ircodes
 154     cmd_MEMADDRESS = BinaryValue("0101")    # 5
 155     cmd_MEMREAD = BinaryValue("0110")       # 6
 156     cmd_MEMREADWRITE = BinaryValue("0111")  # 7
 157
 158     info = "Running Wishbone basic test"
 159     yield from setup_sim(dut, clk_period=clk_period, run=True)
 160     master = yield from setup_jtag(dut, tck_period = tck_period)
 161
 162     # Load the memory address
 163     yield master.load_ir(cmd_MEMADDRESS)
 164     dut._log.info("Loading address")
 165
 166     data_in.binstr = "000000000000000000000000000001"
 167     dut._log.info("  input: {}".format(data_in.binstr))
 168     yield master.shift_data(data_in)
 169     dut._log.info("  output: {}".format(master.result.binstr))
 170
 171     # Do write
 172     yield master.load_ir(cmd_MEMREADWRITE)
 173     dut._log.info("Writing memory")
 174
 175     data_in.binstr = "01010101" * 8
 176     dut._log.info("  input: {}".format(data_in.binstr))
 177     yield master.shift_data(data_in)
 178     dut._log.info("  output: {}".format(master.result.binstr))
 179
 180     data_in.binstr = "10101010" * 8
 181     dut._log.info("  input: {}".format(data_in.binstr))
 182     yield master.shift_data(data_in)
 183     dut._log.info("  output: {}".format(master.result.binstr))
 184
 185     # Load the memory address
 186     yield master.load_ir(cmd_MEMADDRESS)
 187     dut._log.info("Loading address")
 188
 189     data_in.binstr = "000000000000000000000000000001"
 190     dut._log.info("  input: {}".format(data_in.binstr))
 191     yield master.shift_data(data_in)
 192     dut._log.info("  output: {}".format(master.result.binstr))
 193     assert master.result.binstr == "000000000000000000000000000011"
 194
 195     # Do read and write
 196     yield master.load_ir(cmd_MEMREADWRITE)
 197     dut._log.info("Reading and writing memory")
 198
 199     data_in.binstr = "10101010" * 4
 200     dut._log.info("  input: {}".format(data_in.binstr))
 201     yield master.shift_data(data_in)
 202     dut._log.info("  output: {}".format(master.result.binstr))
 203     assert master.result.binstr == "01010101" * 4
 204
 205     data_in.binstr = "01010101" * 4
 206     dut._log.info("  input: {}".format(data_in.binstr))
 207     yield master.shift_data(data_in)
 208     dut._log.info("  output: {}".format(master.result.binstr))
 209     assert master.result.binstr == "10101010" * 4
 210
 211     # Load the memory address
 212     yield master.load_ir(cmd_MEMADDRESS)
 213     dut._log.info("Loading address")
 214
 215     data_in.binstr = "000000000000000000000000000001"
 216     dut._log.info("  input: {}".format(data_in.binstr))
 217     yield master.shift_data(data_in)
 218     dut._log.info("  output: {}".format(master.result.binstr))
 219     assert master.result.binstr == "000000000000000000000000000011"
 220
 221     # Do read
 222     yield master.load_ir(cmd_MEMREAD)
 223     dut._log.info("Reading memory")
 224     data_in.binstr = "00000000" * 4
 225
 226     dut._log.info("  input: {}".format(data_in.binstr))
 227     yield master.shift_data(data_in)
 228     dut._log.info("  output: {}".format(master.result.binstr))
 229     assert master.result.binstr == "10101010" * 4
 230
 231     dut._log.info("  input: {}".format(data_in.binstr))
 232     yield master.shift_data(data_in)
 233     dut._log.info("  output: {}".format(master.result.binstr))
 234     assert master.result.binstr == "01010101" * 4
 235
 236     # Load the memory address
 237     yield master.load_ir(cmd_MEMADDRESS) # MEMADDR
 238     dut._log.info("Loading address")
 239
 240     data_in.binstr = "000000000000000000000000000001"
 241     dut._log.info("  input: {}".format(data_in.binstr))
 242     yield master.shift_data(data_in)
 243     dut._log.info("  output: {}".format(master.result.binstr))
 244     assert master.result.binstr == "000000000000000000000000000011"
 245
 246     # Do read
 247     yield master.load_ir(cmd_MEMREAD) # MEMREAD
 248     dut._log.info("Reading memory")
 249     data_in.binstr = "00000000" * 4
 250
 251     dut._log.info("  input: {}".format(data_in.binstr))
 252     yield master.shift_data(data_in)
 253     dut._log.info("  output: {}".format(master.result.binstr))
 254     assert master.result.binstr == "10101010" * 4
 255
 256     dut._log.info("  input: {}".format(data_in.binstr))
 257     yield master.shift_data(data_in)
 258     dut._log.info("  output: {}".format(master.result.binstr))
 259     assert master.result.binstr == "01010101" * 4
 260
 261     #dut._log.info("{!r}".format(wbmem))
 262
 263
 264 # demo / debug how to get boundary scan names. run "python3 test.py"
 265 if __name__ == '__main__':
 266     pinouts = get_jtag_boundary()
 267     for pin in pinouts:
 268         # example: ('eint', '2', <IOType.In: 1>, 'eint_2', 125)
 269         print (pin)