ls180/post_pnr/cocotb/test.py

   1 import cocotb
   2 from cocotb.clock import Clock
   3 from cocotb.triggers import Timer
   4 from cocotb.utils import get_sim_steps
   5 from cocotb.binary import BinaryValue
   6
   7 from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
   8 from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
   9
  10 #
  11 # Helper functions
  12 #
  13
  14 def setup_sim(dut, *, clk_period, run):
  15     """Initialize CPU and setup clock"""
  16
  17     clk_steps = get_sim_steps(clk_period, "ns")
  18     cocotb.fork(Clock(dut.sys_clk, clk_steps).start())
  19
  20     dut.sys_rst <= 1
  21     dut.sys_clk <= 0
  22     if run:
  23         yield Timer(int(10.5*clk_steps))
  24         dut.sys_rst <= 0
  25         yield Timer(int(5*clk_steps))
  26
  27 def setup_jtag(dut, *, tck_period):
  28     # Make this a generator
  29     if False:
  30         yield Timer(0)
  31     return JTAG_Master(dut.jtag_tck, dut.jtag_tms,
  32                        dut.jtag_tdi, dut.jtag_tdo,
  33                        clk_period=tck_period,
  34                        ir_width=4)
  35
  36 def execute_svf(dut, *, jtag, svf_filename):
  37     jtag_svf = SVF_Executor(jtag)
  38     with open(svf_filename, "r") as f:
  39         svf_deck = f.read()
  40     yield jtag_svf.run(svf_deck, p=dut._log.info)
  41
  42 #
  43 # IDCODE using JTAG_master
  44 #
  45
  46 def idcode(dut, *, jtag):
  47     #jtag.IDCODE = [0, 0, 0, 1]
  48     yield jtag.idcode()
  49     result1 = jtag.result
  50     dut._log.info("IDCODE1: {}".format(result1))
  51     assert(result1 == BinaryValue("00000000000000000001100011111111"))
  52
  53     yield jtag.idcode()
  54     result2 = jtag.result
  55     dut._log.info("IDCODE2: {}".format(result2))
  56
  57     assert(result1 == result2)
  58
  59 @cocotb.test()
  60 def idcode_reset(dut):
  61     dut._log.info("Running IDCODE test; cpu in reset...")
  62
  63     clk_period = 100 # 10MHz
  64     tck_period = 300 # 3MHz
  65
  66     yield from setup_sim(dut, clk_period=clk_period, run=False)
  67     jtag = yield from setup_jtag(dut, tck_period = tck_period)
  68
  69     yield from idcode(dut, jtag=jtag)
  70
  71     dut._log.info("IDCODE test completed")
  72
  73 @cocotb.test()
  74 def idcode_run(dut):
  75     dut._log.info("Running IDCODE test; cpu running...")
  76
  77     clk_period = 100 # 10MHz
  78     tck_period = 300 # 3MHz
  79
  80     yield from setup_sim(dut, clk_period=clk_period, run=True)
  81     jtag = yield from setup_jtag(dut, tck_period = tck_period)
  82
  83     yield from idcode(dut, jtag=jtag)
  84
  85     dut._log.info("IDCODE test completed")
  86
  87 #
  88 # Read IDCODE from SVF file
  89 #
  90
  91 @cocotb.test()
  92 def idcodesvf_reset(dut):
  93     dut._log.info("Running IDCODE through SVF test; cpu in reset...")
  94
  95     clk_period = 100 # 10MHz
  96     tck_period = 300 # 3MHz
  97
  98     yield from setup_sim(dut, clk_period=clk_period, run=False)
  99     jtag = yield from setup_jtag(dut, tck_period = tck_period)
 100
 101     yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
 102
 103     dut._log.info("IDCODE test completed")
 104
 105 @cocotb.test()
 106 def idcode_run(dut):
 107     dut._log.info("Running IDCODE through test; cpu running...")
 108
 109     clk_period = 100 # 10MHz
 110     tck_period = 300 # 3MHz
 111
 112     yield from setup_sim(dut, clk_period=clk_period, run=True)
 113     jtag = yield from setup_jtag(dut, tck_period = tck_period)
 114
 115     yield from execute_svf(dut, jtag=jtag, svf_filename="idcode.svf")
 116
 117     dut._log.info("IDCODE test completed")
 118
 119 from itertools import chain
 120
 121 import cocotb
 122 from cocotb.clock import Clock
 123 from cocotb.triggers import Timer
 124 from cocotb.utils import get_sim_steps
 125 from cocotb.binary import BinaryValue
 126
 127 from c4m.nmigen.jtag.tap import IOType
 128 from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
 129 from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
 130
 131 from soc.config.pinouts import get_pinspecs
 132 from soc.debug.jtag import Pins
 133
 134
 135 @cocotb.test()
 136 def wishbone_basic(dut):
 137     """
 138     Test of an added Wishbone interface
 139     """
 140     clk_period = 100 # 10MHz
 141     tck_period = 3000 # 0.3MHz
 142
 143     data_in = BinaryValue()
 144     # these have to match with soc.debug.jtag.JTAG ircodes
 145     cmd_MEMADDRESS = BinaryValue("0101")    # 5
 146     cmd_MEMREAD = BinaryValue("0110")       # 6
 147     cmd_MEMREADWRITE = BinaryValue("0111")  # 7
 148
 149     info = "Running Wishbone basic test"
 150     yield from setup_sim(dut, clk_period=clk_period, run=True)
 151     master = yield from setup_jtag(dut, tck_period = tck_period)
 152
 153     # Load the memory address
 154     yield master.load_ir(cmd_MEMADDRESS)
 155     dut._log.info("Loading address")
 156
 157     data_in.binstr = "000000000000000000000000000001"
 158     dut._log.info("  input: {}".format(data_in.binstr))
 159     yield master.shift_data(data_in)
 160     dut._log.info("  output: {}".format(master.result.binstr))
 161
 162     # Do write
 163     yield master.load_ir(cmd_MEMREADWRITE)
 164     dut._log.info("Writing memory")
 165
 166     data_in.binstr = "01010101" * 8
 167     dut._log.info("  input: {}".format(data_in.binstr))
 168     yield master.shift_data(data_in)
 169     dut._log.info("  output: {}".format(master.result.binstr))
 170
 171     data_in.binstr = "10101010" * 8
 172     dut._log.info("  input: {}".format(data_in.binstr))
 173     yield master.shift_data(data_in)
 174     dut._log.info("  output: {}".format(master.result.binstr))
 175
 176     # Load the memory address
 177     yield master.load_ir(cmd_MEMADDRESS)
 178     dut._log.info("Loading address")
 179
 180     data_in.binstr = "000000000000000000000000000001"
 181     dut._log.info("  input: {}".format(data_in.binstr))
 182     yield master.shift_data(data_in)
 183     dut._log.info("  output: {}".format(master.result.binstr))
 184     assert master.result.binstr == "000000000000000000000000000000"
 185
 186     # Do read and write
 187     yield master.load_ir(cmd_MEMREADWRITE)
 188     dut._log.info("Reading and writing memory")
 189
 190     data_in.binstr = "10101010" * 4
 191     dut._log.info("  input: {}".format(data_in.binstr))
 192     yield master.shift_data(data_in)
 193     dut._log.info("  output: {}".format(master.result.binstr))
 194     assert master.result.binstr == "01010101" * 4
 195
 196     data_in.binstr = "01010101" * 4
 197     dut._log.info("  input: {}".format(data_in.binstr))
 198     yield master.shift_data(data_in)
 199     dut._log.info("  output: {}".format(master.result.binstr))
 200     assert master.result.binstr == "10101010" * 4
 201
 202     # Load the memory address
 203     yield master.load_ir(cmd_MEMADDRESS)
 204     dut._log.info("Loading address")
 205
 206     data_in.binstr = "000000000000000000000000000001"
 207     dut._log.info("  input: {}".format(data_in.binstr))
 208     yield master.shift_data(data_in)
 209     dut._log.info("  output: {}".format(master.result.binstr))
 210     assert master.result.binstr == "000000000000000000000000000010"
 211
 212     # Do read
 213     yield master.load_ir(cmd_MEMREAD)
 214     dut._log.info("Reading memory")
 215     data_in.binstr = "00000000" * 4
 216
 217     dut._log.info("  input: {}".format(data_in.binstr))
 218     yield master.shift_data(data_in)
 219     dut._log.info("  output: {}".format(master.result.binstr))
 220     assert master.result.binstr == "10101010" * 4
 221
 222     dut._log.info("  input: {}".format(data_in.binstr))
 223     yield master.shift_data(data_in)
 224     dut._log.info("  output: {}".format(master.result.binstr))
 225     assert master.result.binstr == "01010101" * 4
 226
 227     # Load the memory address
 228     yield master.load_ir(cmd_MEMADDRESS) # MEMADDR
 229     dut._log.info("Loading address")
 230
 231     data_in.binstr = "0000000000000000000000000000001"
 232     dut._log.info("  input: {}".format(data_in.binstr))
 233     yield master.shift_data(data_in)
 234     dut._log.info("  output: {}".format(master.result.binstr))
 235     assert master.result.binstr == "000000000000000000000000000010"
 236
 237     # Do read
 238     yield master.load_ir(cmd_MEMREAD) # MEMREAD
 239     dut._log.info("Reading memory")
 240     data_in.binstr = "00000000" * 4
 241
 242     dut._log.info("  input: {}".format(data_in.binstr))
 243     yield master.shift_data(data_in)
 244     dut._log.info("  output: {}".format(master.result.binstr))
 245     assert master.result.binstr == "10101010" * 4
 246
 247     dut._log.info("  input: {}".format(data_in.binstr))
 248     yield master.shift_data(data_in)
 249     dut._log.info("  output: {}".format(master.result.binstr))
 250     assert master.result.binstr == "01010101" * 4
 251
 252     dut._log.info("{!r}".format(wbmem))
 253
 254
 255 # demo / debug how to get boundary scan names. run "python3 test.py"
 256 if __name__ == '__main__':
 257     pinouts = get_jtag_boundary()
 258     for pin in pinouts:
 259         # example: ('eint', '2', <IOType.In: 1>, 'eint_2', 125)
 260         print (pin)