remove wb test from test.py
[soc-cocotb-sim.git] / ls180 / pre_pnr / run_iverilog_ls180.sh
1 #!/bin/sh
2
3 if grep -q ls180sram4k ../../../litex/florent/ls180.v; then
4 top=ls180sram4k
5 else
6 top=ls180
7 fi
8
9 touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
10 # Only run test in reset state as running CPU takes too much time to simulate
11 make \
12 SIM=icarus \
13 TOPLEVEL=$top \
14 COCOTB_RESULTS_FILE=results_iverilog_ls180.xml \
15 COCOTB_HDL_TIMEUNIT=100ps \
16 TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset" \
17 SIM_BUILD=sim_build_iverilog_ls180
18
19