ls180/pre_pnr/run_verilator_wb_ls180.sh

   1 #!/bin/sh
   2
   3 # create dummy memory files
   4 yes 0 | head -128 > mem_1.init
   5 yes 0 | head -32 > mem_1.init
   6 touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
   7
   8 # Only run test in reset state as running CPU takes too much time to simulate
   9 make \
  10   SIM=verilator \
  11   TOPLEVEL=ls180 \
  12   COCOTB_RESULTS_FILE=results_iverilog_ls180_wb.xml \
  13   COCOTB_HDL_TIMEUNIT=100ps \
  14   TESTCASE="wishbone_basic" \
  15   VERILATOR_TRACE="1" \
  16   NOTUSEDCOMPILE_ARGS="--unroll-count 256 \
  17         --output-split 5000 \
  18         --output-split-cfuncs 500 \
  19         --output-split-ctrace 500 \
  20         -Wno-fatal \
  21         -Wno-BLKANDNBLK \
  22         -Wno-WIDTH" \
  23   MODULE="testwb" \
  24   SIM_BUILD=sim_build_iverilator_wb_ls180
  25
  26
  27