b8eed8ec75f7cff464879b50dea890c459eeb3dd
3 YOSYS_INCLUDE
= $(shell yosys-config
--datdir
)/include
9 clang
++ -g
-O3
-std
=c
++14 -I
$(YOSYS_INCLUDE
) $< -o
$@
11 #../../soc/src/soc/litex/florent/libresoc.v \
12 #../../soc/src/soc/litex/florent/ls180.v
14 .
/SPBlock_512W64B8W.v \
18 ls180.
cpp: $(VERILOG_SOURCES
)
19 # create dummy memory files
20 yes
0 | head
-128 > mem.init
21 yes
0 | head
-32 > mem_1.init
23 $(YOSYS
) -p
"read_verilog $?; write_cxxrtl $@"
25 # build verilog from nmigen
30 \rm
-f ls180.
cpp tb ls180.v