projects
/
soc-cxxrtl-sim.git
/ blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
history
|
raw
|
HEAD
add ghdl yosys scripts for compiling ls180
[soc-cxxrtl-sim.git]
/
ls180_test
/
cxxscript.y
1
read_verilog ls180.v libresoc.v SPBlock_512W64B8W.v
2
hierarchy -check -top ls180
3
proc
4
memory
5
write_cxxrtl ls180.cpp