ls180soc.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5 from functools import reduce
   6 from operator import or_
   7
   8 from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState,
   9                    Cat, Record, ClockSignal, wrap, ResetInserter)
  10
  11 from litex.build.generic_platform import Pins, Subsignal
  12 from litex.build.sim import SimPlatform
  13 from litex.build.io import CRG
  14 from litex.build.sim.config import SimConfig
  15
  16 from litex.soc.integration.soc import SoCRegion
  17 from litex.soc.integration.soc_core import SoCCore
  18 from litex.soc.integration.soc_sdram import SoCSDRAM
  19 from litex.soc.integration.builder import Builder
  20 from litex.soc.integration.common import get_mem_data
  21
  22 from litedram import modules as litedram_modules
  23 from litedram.phy.model import SDRAMPHYModel
  24 #from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY
  25 from litedram.common import PHYPadsCombiner, PhySettings
  26 from litedram.phy.dfi import Interface as DFIInterface
  27 from litex.soc.cores.spi import SPIMaster
  28 from litex.soc.cores.pwm import PWM
  29 #from litex.soc.cores.bitbang import I2CMaster
  30 from litex.soc.cores import uart
  31
  32 from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
  33
  34 from litex.tools.litex_sim import Platform
  35 from libresoc.ls180 import LS180Platform
  36
  37 from migen import Module
  38 from litex.soc.interconnect.csr import AutoCSR
  39
  40 from libresoc import LibreSoC
  41 from microwatt import Microwatt
  42
  43 # HACK!
  44 from litex.soc.integration.soc import SoCCSRHandler
  45 SoCCSRHandler.supported_address_width.append(12)
  46 SoCCSRHandler.supported_address_width.append(13)
  47
  48 # GPIO Tristate -------------------------------------------------------
  49 # doesn't work properly.
  50 #from litex.soc.cores.gpio import GPIOTristate
  51 from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField
  52 from migen.genlib.cdc import MultiReg
  53
  54 # Imports
  55 from litex.soc.interconnect import wishbone
  56 from litesdcard.phy import (SDPHY, SDPHYClocker,
  57                             SDPHYInit, SDPHYCMDW, SDPHYCMDR,
  58                             SDPHYDATAW, SDPHYDATAR,
  59                             _sdpads_layout)
  60 from litesdcard.core import SDCore
  61 from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
  62 from litex.build.io import SDROutput, SDRInput
  63
  64
  65 # I2C Master Bit-Banging --------------------------------------------------
  66
  67 class I2CMaster(Module, AutoCSR):
  68     """I2C Master Bit-Banging
  69
  70     Provides the minimal hardware to do software I2C Master bit banging.
  71
  72     On the same write CSRStorage (_w), software can control SCL (I2C_SCL),
  73     SDA direction and value (I2C_OE, I2C_W). Software get back SDA value
  74     with the read CSRStatus (_r).
  75     """
  76     pads_layout = [("scl", 1), ("sda", 1)]
  77     def __init__(self, pads):
  78         self.pads = pads
  79         self._w = CSRStorage(fields=[
  80             CSRField("scl", size=1, offset=0),
  81             CSRField("oe",  size=1, offset=1),
  82             CSRField("sda", size=1, offset=2)],
  83             name="w")
  84         self._r = CSRStatus(fields=[
  85             CSRField("sda", size=1, offset=0)],
  86             name="r")
  87
  88         self.connect(pads)
  89
  90     def connect(self, pads):
  91         _sda_w  = Signal()
  92         _sda_oe = Signal()
  93         _sda_r  = Signal()
  94         self.comb += [
  95             pads.scl.eq(self._w.fields.scl),
  96             pads.sda_oe.eq( self._w.fields.oe),
  97             pads.sda_o.eq(  self._w.fields.sda),
  98             self._r.fields.sda.eq(pads.sda_i),
  99         ]
 100
 101
 102 class GPIOTristateASIC(Module, AutoCSR):
 103     def __init__(self, name, pads, prange=None):
 104         if prange is None:
 105             prange = range(nbits)
 106         nbits     = len(prange)
 107
 108         self._oe  = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
 109         self._in  = CSRStatus(nbits,  description="GPIO Input(s) Status.")
 110         self._out = CSRStorage(nbits, description="GPIO Ouptut(s) Control.")
 111
 112         # # #
 113
 114         _pads = Record( ((name+"i",  nbits),
 115                          (name+"o",  nbits),
 116                          (name+"oe", nbits)))
 117         _o = getattr(_pads, name+"o")
 118         _oe = getattr(_pads, name+"oe")
 119         _i = getattr(_pads, name+"i")
 120         for j, i in enumerate(prange):
 121             self.comb += _i[j].eq(pads.i[i])
 122             self.comb += pads.o[i].eq(_o[j])
 123             self.comb += pads.oe[i].eq(_oe[j])
 124
 125         clk = ClockSignal()
 126         o = self._out.storage
 127         oe = self._oe.storage
 128         i = self._in.status
 129         for j in range(nbits):
 130             self.specials += SDROutput(clk=clk, i=oe[j], o=_oe[j])
 131             self.specials += SDROutput(clk=clk, i=o[j], o=_o[j])
 132             self.specials += SDRInput(clk=clk, i=_i[j], o=i[j])
 133         #for i in range(nbits):
 134             #self.comb += _pads.oe[i].eq(self._oe.storage[i])
 135             #self.comb += _pads.o[i].eq(self._out.storage[i])
 136             #self.specials += MultiReg(_pads.i[i], self._in.status[i])
 137
 138 # SDCard PHY IO -------------------------------------------------------
 139
 140 class SDRPad(Module):
 141     def __init__(self, pad, name, o, oe, i):
 142         clk = ClockSignal()
 143         _o = getattr(pad, "%s_o" % name)
 144         _oe = getattr(pad, "%s_oe" % name)
 145         _i = getattr(pad, "%s_i" % name)
 146         for j in range(len(_o)):
 147             self.specials += SDROutput(clk=clk, i=oe, o=_oe[j])
 148             self.specials += SDROutput(clk=clk, i=o[j], o=_o[j])
 149             self.specials += SDRInput(clk=clk, i=_i[j], o=i[j])
 150
 151
 152 class SDPHYIOGen(Module):
 153     def __init__(self, clocker, sdpads, pads):
 154         # Rst
 155         if hasattr(pads, "rst"):
 156             self.comb += pads.rst.eq(0)
 157
 158         # Clk
 159         self.specials += SDROutput(
 160             clk = ClockSignal(),
 161             i   = ~clocker.clk & sdpads.clk,
 162             o   = pads.clk
 163         )
 164
 165         # Cmd
 166         c = sdpads.cmd
 167         self.submodules.sd_cmd = SDRPad(pads, "cmd", c.o, c.oe, c.i)
 168
 169         # Data
 170         d = sdpads.data
 171         self.submodules.sd_data = SDRPad(pads, "data", d.o, d.oe, d.i)
 172
 173
 174 class SDPHY(Module, AutoCSR):
 175     def __init__(self, pads, device, sys_clk_freq,
 176                  cmd_timeout=10e-3, data_timeout=10e-3):
 177         self.card_detect = CSRStatus() # Assume SDCard is present if no cd pin.
 178         self.comb += self.card_detect.status.eq(getattr(pads, "cd", 0))
 179
 180         self.submodules.clocker = clocker = SDPHYClocker()
 181         self.submodules.init    = init    = SDPHYInit()
 182         self.submodules.cmdw    = cmdw    = SDPHYCMDW()
 183         self.submodules.cmdr    = cmdr    = SDPHYCMDR(sys_clk_freq,
 184                                                       cmd_timeout, cmdw)
 185         self.submodules.dataw   = dataw   = SDPHYDATAW()
 186         self.submodules.datar   = datar   = SDPHYDATAR(sys_clk_freq,
 187                                                       data_timeout)
 188
 189         # # #
 190
 191         self.sdpads = sdpads = Record(_sdpads_layout)
 192
 193         # IOs
 194         sdphy_cls = SDPHYIOGen
 195         self.submodules.io = sdphy_cls(clocker, sdpads, pads)
 196
 197         # Connect pads_out of submodules to physical pads --------------
 198         pl = [init, cmdw, cmdr, dataw, datar]
 199         self.comb += [
 200             sdpads.clk.eq(    reduce(or_, [m.pads_out.clk     for m in pl])),
 201             sdpads.cmd.oe.eq( reduce(or_, [m.pads_out.cmd.oe  for m in pl])),
 202             sdpads.cmd.o.eq(  reduce(or_, [m.pads_out.cmd.o   for m in pl])),
 203             sdpads.data.oe.eq(reduce(or_, [m.pads_out.data.oe for m in pl])),
 204             sdpads.data.o.eq( reduce(or_, [m.pads_out.data.o  for m in pl])),
 205         ]
 206         for m in pl:
 207             self.comb += m.pads_out.ready.eq(self.clocker.ce)
 208
 209         # Connect physical pads to pads_in of submodules ---------------
 210         for m in pl:
 211             self.comb += m.pads_in.valid.eq(self.clocker.ce)
 212             self.comb += m.pads_in.cmd.i.eq(sdpads.cmd.i)
 213             self.comb += m.pads_in.data.i.eq(sdpads.data.i)
 214
 215         # Speed Throttling -------------------------------------------
 216         self.comb += clocker.stop.eq(dataw.stop | datar.stop)
 217
 218
 219 # Generic SDR PHY ---------------------------------------------------------
 220
 221 class GENSDRPHY(Module):
 222     def __init__(self, pads, cl=2, cmd_latency=1):
 223         pads        = PHYPadsCombiner(pads)
 224         addressbits = len(pads.a)
 225         bankbits    = len(pads.ba)
 226         nranks      = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
 227         databits    = len(pads.dq_i)
 228         assert cl in [2, 3]
 229         assert databits%8 == 0
 230
 231         # PHY settings ----------------------------------------------------
 232         self.settings = PhySettings(
 233             phytype       = "GENSDRPHY",
 234             memtype       = "SDR",
 235             databits      = databits,
 236             dfi_databits  = databits,
 237             nranks        = nranks,
 238             nphases       = 1,
 239             rdphase       = 0,
 240             wrphase       = 0,
 241             rdcmdphase    = 0,
 242             wrcmdphase    = 0,
 243             cl            = cl,
 244             read_latency  = cl + cmd_latency,
 245             write_latency = 0
 246         )
 247
 248         # DFI Interface ---------------------------------------------------
 249         self.dfi = dfi = DFIInterface(addressbits, bankbits, nranks, databits)
 250
 251         # # #
 252
 253         # Iterate on pads groups ------------------------------------------
 254         for pads_group in range(len(pads.groups)):
 255             pads.sel_group(pads_group)
 256
 257             # Addresses and Commands --------------------------------------
 258             p0 = dfi.p0
 259             self.specials += [SDROutput(i=p0.address[i], o=pads.a[i])
 260                                     for i in range(len(pads.a))]
 261             self.specials += [SDROutput(i=p0.bank[i], o=pads.ba[i])
 262                                     for i in range(len(pads.ba))]
 263             self.specials += SDROutput(i=p0.cas_n, o=pads.cas_n)
 264             self.specials += SDROutput(i=p0.ras_n, o=pads.ras_n)
 265             self.specials += SDROutput(i=p0.we_n, o=pads.we_n)
 266             if hasattr(pads, "cke"):
 267                 for i in range(len(pads.cke)):
 268                         self.specials += SDROutput(i=p0.cke[i], o=pads.cke[i])
 269             if hasattr(pads, "cs_n"):
 270                 for i in range(len(pads.cs_n)):
 271                     self.specials += SDROutput(i=p0.cs_n[i], o=pads.cs_n[i])
 272
 273         # DQ/DM Data Path -------------------------------------------------
 274
 275         d = dfi.p0
 276         wren = []
 277         self.submodules.dq = SDRPad(pads, "dq", d.wrdata, d.wrdata_en, d.rddata)
 278
 279         if hasattr(pads, "dm"):
 280             print ("sdr pads dm len", pads.dm, len(pads.dm))
 281             for i in range(len(pads.dm)):
 282                 self.specials += SDROutput(i=d.wrdata_en&d.wrdata_mask[i],
 283                                            o=pads.dm[i])
 284
 285         # DQ/DM Control Path ----------------------------------------------
 286         rddata_en = Signal(cl + cmd_latency)
 287         self.sync += rddata_en.eq(Cat(dfi.p0.rddata_en, rddata_en))
 288         self.sync += dfi.p0.rddata_valid.eq(rddata_en[-1])
 289
 290
 291 # LibreSoC 180nm ASIC -------------------------------------------------------
 292
 293 class LibreSoCSim(SoCCore):
 294     def __init__(self, cpu="libresoc", debug=False, with_sdram=True,
 295             sdram_module          = "AS4C16M16",
 296             #sdram_data_width      = 16,
 297             #sdram_module          = "MT48LC16M16",
 298             sdram_data_width      = 16,
 299             irq_reserved_irqs = {'uart': 0},
 300             platform='sim',
 301             dff_srams=5,
 302             srams_4k=False,
 303             ):
 304         assert cpu in ["libresoc", "microwatt"]
 305         sys_clk_freq = int(50e6)
 306
 307         platform_name = platform
 308         if platform == 'sim':
 309             platform     = Platform()
 310             self.platform.name = 'ls180'
 311             uart_name = "sim"
 312         elif 'ls180' in platform:
 313             platform     = LS180Platform()
 314             uart_name = "uart"
 315
 316         #cpu_data_width = 32
 317         cpu_data_width = 64
 318
 319         if srams_4k:
 320             variant = "ls180sram4k"
 321         else:
 322             variant = "ls180nopll"
 323
 324         print ("CPU, variant", platform_name, variant)
 325
 326         # reserve XICS ICP and XICS memory addresses.
 327         self.mem_map['xics_icp']  = 0xc0010000
 328         self.mem_map['xics_ics']  = 0xc0011000
 329         #self.csr_map["icp"] = 8  #  8 x 0x800 == 0x4000
 330         #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
 331
 332         ram_init = []
 333         if False:
 334             #ram_init = get_mem_data({
 335             #    ram_fname:       "0x00000000",
 336             #    }, "little")
 337             ram_init = get_mem_data(ram_fname, "little")
 338
 339             # remap the main RAM to reset-start-address
 340
 341             # without sram nothing works, therefore move it to higher up
 342             self.mem_map["sram"] = 0x90000000
 343
 344             # put UART at 0xc000200 (w00t!  this works!)
 345             self.csr_map["uart"] = 4
 346
 347         self.mem_map["main_ram"] = 0x90000000
 348         if dff_srams == 5:
 349             self.mem_map["sram"] = 0x00000000
 350             self.mem_map["sram1"] = 0x00000200
 351             self.mem_map["sram2"] = 0x00000400
 352             self.mem_map["sram3"] = 0x00000600
 353             self.mem_map["sram4"] = 0x00000800
 354             sram_size = 0x200
 355         else:
 356             sram_size = 0x80 # ridiculously small
 357             if "sram4k" not in variant:
 358                 sram_size = 0x200 # no 4k SRAMs, make slightly bigger
 359             self.mem_map["sram"] = 0x00000000
 360             self.mem_map["sram1"] = 0x00000700
 361         self.mem_map["sram4k_0"] = 0x00001000
 362         self.mem_map["sram4k_1"] = 0x00002000
 363         self.mem_map["sram4k_2"] = 0x00003000
 364         self.mem_map["sram4k_3"] = 0x00004000
 365
 366         # SoCCore -------------------------------------------------------------
 367         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
 368             cpu_type                 = "microwatt",
 369             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
 370                                        else Microwatt,
 371             #bus_data_width           = 64, # don't add this! stops conversion
 372             csr_address_width        = 13, # limit to 0x8000
 373             cpu_variant              = variant,
 374             csr_data_width            = 8,
 375             l2_size             = 0,
 376             with_uart                = False,
 377             uart_name                = None,
 378             with_sdram               = with_sdram,
 379             sdram_module          = sdram_module,
 380             sdram_data_width      = sdram_data_width,
 381             integrated_rom_size      = 0, # if ram_fname else 0x10000,
 382             #integrated_sram_size     = 0x1000, - problem with yosys ABC
 383             integrated_sram_size     = sram_size,
 384             #integrated_main_ram_init  = ram_init,
 385             integrated_main_ram_size = 0x00000000 if with_sdram \
 386                                         else 0x10000000 , # 256MB
 387             )
 388
 389         self.platform.name = platform_name
 390
 391         if dff_srams == 5:
 392             # add 4 more 4k integrated SRAMs
 393             self.add_ram("sram1", self.mem_map["sram1"], 0x200)
 394             self.add_ram("sram2", self.mem_map["sram2"], 0x200)
 395             self.add_ram("sram3", self.mem_map["sram3"], 0x200)
 396             self.add_ram("sram4", self.mem_map["sram4"], 0x200)
 397         else:
 398             self.add_ram("sram1", self.mem_map["sram1"], 0x80) # tiny!
 399
 400         # SDR SDRAM ----------------------------------------------
 401         if False: # not self.integrated_main_ram_size:
 402             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
 403
 404         if cpu == "libresoc":
 405             # XICS interrupt devices
 406             icp_addr = self.mem_map['xics_icp']
 407             icp_wb = self.cpu.xics_icp
 408             icp_region = SoCRegion(origin=icp_addr, size=0x20, cached=False)
 409             self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
 410
 411             ics_addr = self.mem_map['xics_ics']
 412             ics_wb = self.cpu.xics_ics
 413             ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
 414             self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
 415
 416             # add 4x 4k SRAMs
 417             for i, sram_wb in enumerate(self.cpu.srams):
 418                 name = 'sram4k_%d' % i
 419                 sram_adr = self.mem_map[name]
 420                 ics_region = SoCRegion(origin=sram_adr, size=0x1000)
 421                 self.bus.add_slave(name=name, slave=sram_wb, region=ics_region)
 422
 423         # CRG -----------------------------------------------------------------
 424         self.submodules.crg = CRG(platform.request("sys_clk"),
 425                                   platform.request("sys_rst"))
 426
 427         if hasattr(self.cpu, "clk_sel"):
 428             # PLL/Clock Select
 429             clksel_i = platform.request("sys_clksel_i")
 430             pll_test_o = platform.request("sys_pll_testout_o")
 431             pll_vco_o = platform.request("sys_pll_vco_o")
 432
 433             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
 434             self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL
 435             self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag
 436
 437         #ram_init = []
 438
 439         # SDRAM ----------------------------------------------------
 440         if with_sdram:
 441             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
 442             sdram_module_cls = getattr(litedram_modules, sdram_module)
 443             sdram_rate       = "1:{}".format(
 444                     sdram_module_nphases[sdram_module_cls.memtype])
 445             sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
 446             phy_settings     = get_sdram_phy_settings(
 447                             memtype    = sdram_module.memtype,
 448                             data_width = sdram_data_width,
 449                             clk_freq   = sdram_clk_freq)
 450             #sdrphy_cls = HalfRateGENSDRPHY
 451             sdrphy_cls = GENSDRPHY
 452             sdram_pads = self.cpu.cpupads['sdr']
 453             self.submodules.sdrphy = sdrphy_cls(sdram_pads)
 454             #self.submodules.sdrphy = sdrphy_cls(sdram_module,
 455             #                                       phy_settings,
 456             #                                       init=ram_init
 457             #                                        )
 458             self.add_sdram("sdram",
 459                 phy                     = self.sdrphy,
 460                 module                  = sdram_module,
 461                 origin                  = self.mem_map["main_ram"],
 462                 size                    = 0x80000000,
 463                 l2_cache_size           = 0, # 8192
 464                 l2_cache_min_data_width = 128,
 465                 l2_cache_reverse        = True
 466             )
 467             # FIXME: skip memtest to avoid corrupting memory
 468             self.add_constant("MEMTEST_BUS_SIZE",  128//16)
 469             self.add_constant("MEMTEST_DATA_SIZE", 128//16)
 470             self.add_constant("MEMTEST_ADDR_SIZE", 128//16)
 471             self.add_constant("MEMTEST_BUS_DEBUG", 1)
 472             self.add_constant("MEMTEST_ADDR_DEBUG", 1)
 473             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 474
 475             # SDRAM clock
 476             sys_clk = ClockSignal()
 477             #sdr_clk = self.cpu.cpupads['sdram_clock']
 478             sdr_clk = sdram_pads.clock
 479             #self.specials += DDROutput(1, 0, , sdram_clk)
 480             self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
 481
 482         # UART
 483         uart_core_pads = self.cpu.cpupads['uart']
 484         self.submodules.uart_phy = uart.UARTPHY(
 485                 pads     = uart_core_pads,
 486                 clk_freq = self.sys_clk_freq,
 487                 baudrate = 115200)
 488         self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
 489                 tx_fifo_depth = 16,
 490                 rx_fifo_depth = 16))
 491
 492         self.csr.add("uart_phy", use_loc_if_exists=True)
 493         self.csr.add("uart", use_loc_if_exists=True)
 494         self.irq.add("uart", use_loc_if_exists=True)
 495
 496         # GPIOs (bi-directional)
 497         gpio_core_pads = self.cpu.cpupads['gpio']
 498         self.submodules.gpio0 = GPIOTristateASIC("gpio0", gpio_core_pads,
 499                                                  range(8))
 500         self.add_csr("gpio0")
 501
 502         self.submodules.gpio1 = GPIOTristateASIC("gpio1", gpio_core_pads,
 503                                                  range(8, 16))
 504         self.add_csr("gpio1")
 505
 506         # SPI Master
 507         print ("cpupadkeys", self.cpu.cpupads.keys())
 508         if hasattr(self.cpu.cpupads, 'mspi0'):
 509             sd_clk_freq = 8e6
 510             pads = self.cpu.cpupads['mspi0']
 511             spimaster = SPIMaster(pads, 8, self.sys_clk_freq, sd_clk_freq)
 512             spimaster.add_clk_divider()
 513             setattr(self.submodules, 'spimaster', spimaster)
 514             self.add_csr('spimaster')
 515
 516         if hasattr(self.cpu.cpupads, 'mspi1'):
 517             # SPI SDCard (1 wide)
 518             spi_clk_freq = 400e3
 519             pads = self.cpu.cpupads['mspi1']
 520             spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
 521             spisdcard.add_clk_divider()
 522             setattr(self.submodules, 'spisdcard', spisdcard)
 523             self.add_csr('spisdcard')
 524
 525         # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
 526         eintpads = self.cpu.cpupads['eint']
 527         print ("eintpads", eintpads)
 528         self.eint_tmp = Signal(len(eintpads))
 529         for i in range(len(eintpads)):
 530             self.comb += self.cpu.interrupt[13+i].eq(self.eint_tmp[i])
 531             self.comb += self.eint_tmp[i].eq(getattr(eintpads, "%d" % i))
 532
 533         # JTAG
 534         jtagpads = platform.request("jtag")
 535         self.comb += self.cpu.jtag_tck.eq(jtagpads.tck)
 536         self.comb += self.cpu.jtag_tms.eq(jtagpads.tms)
 537         self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
 538         self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
 539
 540         # NC - allows some iopads to be connected up
 541         # sigh, just do something, anything, to stop yosys optimising these out
 542         nc_pads = platform.request("nc")
 543         num_nc = len(nc_pads)
 544         self.nc = Signal(num_nc)
 545         self.comb += self.nc.eq(nc_pads)
 546         self.dummy = Signal(num_nc)
 547         for i in range(num_nc):
 548             self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0])
 549
 550         # PWM
 551         if hasattr(self.cpu.cpupads, 'pwm'):
 552             pwmpads = self.cpu.cpupads['pwm']
 553             for i in range(2):
 554                 name = "pwm%d" % i
 555                 setattr(self.submodules, name, PWM(pwmpads[i]))
 556                 self.add_csr(name)
 557
 558         # I2C Master
 559         i2c_core_pads = self.cpu.cpupads['mtwi']
 560         self.submodules.i2c = I2CMaster(i2c_core_pads)
 561         self.add_csr("i2c")
 562
 563         # SDCard -----------------------------------------------------
 564
 565         if hasattr(self.cpu.cpupads, 'sd0'):
 566             # Emulator / Pads
 567             sdcard_pads = self.cpu.cpupads['sd0']
 568
 569             # Core
 570             self.submodules.sdphy  = SDPHY(sdcard_pads,
 571                                            self.platform.device, self.clk_freq)
 572             self.submodules.sdcore = SDCore(self.sdphy)
 573             self.add_csr("sdphy")
 574             self.add_csr("sdcore")
 575
 576             # Block2Mem DMA
 577             bus = wishbone.Interface(data_width=self.bus.data_width,
 578                                      adr_width=self.bus.address_width)
 579             self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus,
 580                                         endianness=self.cpu.endianness)
 581             self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
 582             dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
 583             dma_bus.add_master("sdblock2mem", master=bus)
 584             self.add_csr("sdblock2mem")
 585
 586             # Mem2Block DMA
 587             bus = wishbone.Interface(data_width=self.bus.data_width,
 588                                      adr_width=self.bus.address_width)
 589             self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus,
 590                                                 endianness=self.cpu.endianness)
 591             self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
 592             dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
 593             dma_bus.add_master("sdmem2block", master=bus)
 594             self.add_csr("sdmem2block")
 595
 596         # Debug ---------------------------------------------------------------
 597         if not debug:
 598             return
 599
 600         jtag_en = ('jtag' in variant) or ('ls180' in variant)
 601
 602         # setup running of DMI FSM
 603         dmi_addr = Signal(4)
 604         dmi_din = Signal(64)
 605         dmi_dout = Signal(64)
 606         dmi_wen = Signal(1)
 607         dmi_req = Signal(1)
 608
 609         # debug log out
 610         dbg_addr = Signal(4)
 611         dbg_dout = Signal(64)
 612         dbg_msg = Signal(1)
 613
 614         # capture pc from dmi
 615         pc = Signal(64)
 616         active_dbg = Signal()
 617         active_dbg_cr = Signal()
 618         active_dbg_xer = Signal()
 619
 620         # xer flags
 621         xer_so = Signal()
 622         xer_ca = Signal()
 623         xer_ca32 = Signal()
 624         xer_ov = Signal()
 625         xer_ov32 = Signal()
 626
 627         # increment counter, Stop after 100000 cycles
 628         uptime = Signal(64)
 629         self.sync += uptime.eq(uptime + 1)
 630         #self.sync += If(uptime == 1000000000000, Finish())
 631
 632         # DMI FSM counter and FSM itself
 633         dmicount = Signal(10)
 634         dmirunning = Signal(1)
 635         dmi_monitor = Signal(1)
 636         dmifsm = FSM()
 637         self.submodules += dmifsm
 638
 639         # DMI FSM
 640         dmifsm.act("START",
 641             If(dmi_req & dmi_wen,
 642                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 643                  self.cpu.dmi_din.eq(dmi_din), # DMI in
 644                  self.cpu.dmi_req.eq(1),    # DMI request
 645                  self.cpu.dmi_wr.eq(1),    # DMI write
 646                  If(self.cpu.dmi_ack,
 647                     (NextState("IDLE"),
 648                     )
 649                  ),
 650                 ),
 651             ),
 652             If(dmi_req & ~dmi_wen,
 653                 (self.cpu.dmi_addr.eq(dmi_addr),   # DMI Addr
 654                  self.cpu.dmi_req.eq(1),    # DMI request
 655                  self.cpu.dmi_wr.eq(0),    # DMI read
 656                  If(self.cpu.dmi_ack,
 657                     # acknowledge received: capture data.
 658                     (NextState("IDLE"),
 659                      NextValue(dbg_addr, dmi_addr),
 660                      NextValue(dbg_dout, self.cpu.dmi_dout),
 661                      NextValue(dbg_msg, 1),
 662                     ),
 663                  ),
 664                 ),
 665             )
 666         )
 667
 668         # DMI response received: reset the dmi request and check if
 669         # in "monitor" mode
 670         dmifsm.act("IDLE",
 671             If(dmi_monitor,
 672                  NextState("FIRE_MONITOR"), # fire "monitor" on next cycle
 673             ).Else(
 674                  NextState("START"), # back to start on next cycle
 675             ),
 676             NextValue(dmi_req, 0),
 677             NextValue(dmi_addr, 0),
 678             NextValue(dmi_din, 0),
 679             NextValue(dmi_wen, 0),
 680         )
 681
 682         # "monitor" mode fires off a STAT request
 683         dmifsm.act("FIRE_MONITOR",
 684             (NextValue(dmi_req, 1),
 685              NextValue(dmi_addr, 1), # DMI STAT address
 686              NextValue(dmi_din, 0),
 687              NextValue(dmi_wen, 0), # read STAT
 688              NextState("START"), # back to start on next cycle
 689             )
 690         )
 691
 692         self.comb += xer_so.eq((dbg_dout & 1) == 1)
 693         self.comb += xer_ca.eq((dbg_dout & 4) == 4)
 694         self.comb += xer_ca32.eq((dbg_dout & 8) == 8)
 695         self.comb += xer_ov.eq((dbg_dout & 16) == 16)
 696         self.comb += xer_ov32.eq((dbg_dout & 32) == 32)
 697
 698         # debug messages out
 699         self.sync += If(dbg_msg,
 700             (If(active_dbg & (dbg_addr == 0b10), # PC
 701                 Display("pc : %016x", dbg_dout),
 702              ),
 703              If(dbg_addr == 0b10, # PC
 704                  pc.eq(dbg_dout),     # capture PC
 705              ),
 706              #If(dbg_addr == 0b11, # MSR
 707              #   Display("    msr: %016x", dbg_dout),
 708              #),
 709              If(dbg_addr == 0b1000, # CR
 710                 Display("    cr : %016x", dbg_dout),
 711              ),
 712              If(dbg_addr == 0b1001, # XER
 713                 Display("    xer: so %d ca %d 32 %d ov %d 32 %d",
 714                             xer_so, xer_ca, xer_ca32, xer_ov, xer_ov32),
 715              ),
 716              If(dbg_addr == 0b101, # GPR
 717                 Display("    gpr: %016x", dbg_dout),
 718              ),
 719             # also check if this is a "stat"
 720             If(dbg_addr == 1, # requested a STAT
 721                 #Display("    stat: %x", dbg_dout),
 722                 If(dbg_dout & 2, # bit 2 of STAT is "stopped" mode
 723                      dmirunning.eq(1), # continue running
 724                      dmi_monitor.eq(0), # and stop monitor mode
 725                 ),
 726             ),
 727              dbg_msg.eq(0)
 728             )
 729         )
 730
 731         # kick off a "stop"
 732         self.sync += If(uptime == 0,
 733             (dmi_addr.eq(0), # CTRL
 734              dmi_din.eq(1<<0), # STOP
 735              dmi_req.eq(1),
 736              dmi_wen.eq(1),
 737             )
 738         )
 739
 740         self.sync += If(uptime == 4,
 741              dmirunning.eq(1),
 742         )
 743
 744         self.sync += If(dmirunning,
 745              dmicount.eq(dmicount + 1),
 746         )
 747
 748         # loop every 1<<N cycles
 749         cyclewid = 9
 750
 751         # get the PC
 752         self.sync += If(dmicount == 4,
 753             (dmi_addr.eq(0b10), # NIA
 754              dmi_req.eq(1),
 755              dmi_wen.eq(0),
 756             )
 757         )
 758
 759         # kick off a "step"
 760         self.sync += If(dmicount == 8,
 761             (dmi_addr.eq(0), # CTRL
 762              dmi_din.eq(1<<3), # STEP
 763              dmi_req.eq(1),
 764              dmi_wen.eq(1),
 765              dmirunning.eq(0), # stop counter, need to fire "monitor"
 766              dmi_monitor.eq(1), # start "monitor" instead
 767             )
 768         )
 769
 770         # limit range of pc for debug reporting
 771         #self.comb += active_dbg.eq((0x378c <= pc) & (pc <= 0x38d8))
 772         #self.comb += active_dbg.eq((0x0 < pc) & (pc < 0x58))
 773         self.comb += active_dbg.eq(1)
 774
 775
 776         # get the MSR
 777         self.sync += If(active_dbg & (dmicount == 12),
 778             (dmi_addr.eq(0b11), # MSR
 779              dmi_req.eq(1),
 780              dmi_wen.eq(0),
 781             )
 782         )
 783
 784         if cpu == "libresoc":
 785             #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
 786             self.comb += active_dbg_cr.eq(0)
 787
 788             # get the CR
 789             self.sync += If(active_dbg_cr & (dmicount == 16),
 790                 (dmi_addr.eq(0b1000), # CR
 791                  dmi_req.eq(1),
 792                  dmi_wen.eq(0),
 793                 )
 794             )
 795
 796             #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
 797             self.comb += active_dbg_xer.eq(active_dbg_cr)
 798
 799             # get the CR
 800             self.sync += If(active_dbg_xer & (dmicount == 20),
 801                 (dmi_addr.eq(0b1001), # XER
 802                  dmi_req.eq(1),
 803                  dmi_wen.eq(0),
 804                 )
 805             )
 806
 807         # read all 32 GPRs
 808         for i in range(32):
 809             self.sync += If(active_dbg & (dmicount == 24+(i*8)),
 810                 (dmi_addr.eq(0b100), # GSPR addr
 811                  dmi_din.eq(i), # r1
 812                  dmi_req.eq(1),
 813                  dmi_wen.eq(1),
 814                 )
 815             )
 816
 817             self.sync += If(active_dbg & (dmicount == 28+(i*8)),
 818                 (dmi_addr.eq(0b101), # GSPR data
 819                  dmi_req.eq(1),
 820                  dmi_wen.eq(0),
 821                 )
 822             )
 823
 824         # monitor bbus read/write
 825         self.sync += If(active_dbg & self.cpu.dbus.stb & self.cpu.dbus.ack,
 826             Display("    [%06x] dadr: %8x, we %d s %01x w %016x r: %016x",
 827                 #uptime,
 828                 0,
 829                 self.cpu.dbus.adr,
 830                 self.cpu.dbus.we,
 831                 self.cpu.dbus.sel,
 832                 self.cpu.dbus.dat_w,
 833                 self.cpu.dbus.dat_r
 834             )
 835         )
 836
 837         return
 838
 839         # monitor ibus write
 840         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 841                         self.cpu.ibus.we,
 842             Display("    [%06x] iadr: %8x, s %01x w %016x",
 843                 #uptime,
 844                 0,
 845                 self.cpu.ibus.adr,
 846                 self.cpu.ibus.sel,
 847                 self.cpu.ibus.dat_w,
 848             )
 849         )
 850         # monitor ibus read
 851         self.sync += If(active_dbg & self.cpu.ibus.stb & self.cpu.ibus.ack &
 852                         ~self.cpu.ibus.we,
 853             Display("    [%06x] iadr: %8x, s %01x r %016x",
 854                 #uptime,
 855                 0,
 856                 self.cpu.ibus.adr,
 857                 self.cpu.ibus.sel,
 858                 self.cpu.ibus.dat_r
 859             )
 860         )
 861
 862 # Build -----------------------------------------------------------------------
 863
 864 def main():
 865     parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
 866     parser.add_argument("--cpu",          default="libresoc",
 867                         help="CPU to use: libresoc (default) or microwatt")
 868     parser.add_argument("--platform",     default="sim",
 869                         help="platform (sim or ls180)")
 870     parser.add_argument("--debug",        action="store_true",
 871                         help="Enable debug traces")
 872     parser.add_argument("--trace",        action="store_true",
 873                         help="Enable tracing")
 874     parser.add_argument("--trace-start",  default=0,
 875                         help="Cycle to start FST tracing")
 876     parser.add_argument("--trace-end",    default=-1,
 877                         help="Cycle to end FST tracing")
 878     parser.add_argument("--num-srams",    default=5,
 879                         help="number of srams")
 880     parser.add_argument("--srams4k",    action="store_true",
 881                         help="enable 4k srams")
 882     parser.add_argument("--build", action="store_true", help="Build bitstream")
 883     args = parser.parse_args()
 884
 885     print ("number of SRAMs", args.num_srams)
 886     print ("enable 4K SRAMs variant", args.srams4k)
 887
 888     if 'ls180' in args.platform:
 889         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
 890                           platform=args.platform,
 891                           srams_4k=args.srams4k,
 892                           dff_srams=args.num_srams)
 893         builder = Builder(soc, compile_gateware = True)
 894         builder.build(run         = True)
 895         os.chdir("../")
 896     else:
 897
 898         sim_config = SimConfig(default_clk="sys_clk")
 899         sim_config.add_module("serial2console", "serial")
 900
 901         for i in range(2):
 902             soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
 903                               platform=args.platform,
 904                               dff_srams=args.num_srams)
 905             builder = Builder(soc, compile_gateware = i!=0)
 906             builder.build(sim_config=sim_config,
 907                 run         = i!=0,
 908                 trace       = args.trace,
 909                 trace_start = int(args.trace_start),
 910                 trace_end   = int(args.trace_end),
 911                 trace_fst   = 0)
 912             os.chdir("../")
 913
 914 if __name__ == "__main__":
 915     main()