manual/CHAPTER_Appnotes.tex

   1
   2 \chapter{Application Notes}
   3 \label{chapter:appnotes}
   4
   5 % \begin{fixme}
   6 % This appendix will cover some typical use-cases of Yosys in the form of application notes.
   7 % \end{fixme}
   8 %
   9 % \section{Synthesizing using a Cell Library in Liberty Format}
  10 % \section{Reverse Engineering the MOS6502 from an NMOS Transistor Netlist}
  11 % \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
  12
  13 This appendix contains copies of the Yosys application notes.
  14
  15 \begin{itemize}
  16 \item Yosys AppNote 010: Converting Verilog to BLIF \dotfill Page \pageref{app:010} \hskip2cm\null
  17 \item Yosys AppNote 011: Interactive Design Investigation \dotfill Page \pageref{app:011} \hskip2cm\null
  18 \item Yosys AppNote 012: Converting Verilog to BTOR \dotfill Page \pageref{app:012} \hskip2cm\null
  19 \end{itemize}
  20
  21 \eject\label{app:010}
  22 \includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_010_Verilog_to_BLIF.pdf}
  23
  24 \eject\label{app:011}
  25 \includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_011_Design_Investigation.pdf}
  26
  27 \eject\label{app:012}
  28 \includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_012_Verilog_to_BTOR.pdf}
  29