microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countzero.vhdl
  22       - gpr_hazard.vhdl
  23       - cr_hazard.vhdl
  24       - control.vhdl
  25       - execute1.vhdl
  26       - fpu.vhdl
  27       - loadstore1.vhdl
  28       - mmu.vhdl
  29       - dcache.vhdl
  30       - divider.vhdl
  31       - rotator.vhdl
  32       - writeback.vhdl
  33       - insn_helpers.vhdl
  34       - core.vhdl
  35       - icache.vhdl
  36       - plru.vhdl
  37       - cache_ram.vhdl
  38       - core_debug.vhdl
  39       - utils.vhdl
  40     file_type : vhdlSource-2008
  41
  42   soc:
  43     files:
  44       - wishbone_arbiter.vhdl
  45       - wishbone_debug_master.vhdl
  46       - wishbone_bram_wrapper.vhdl
  47       - soc.vhdl
  48       - xics.vhdl
  49       - syscon.vhdl
  50       - sync_fifo.vhdl
  51       - spi_rxtx.vhdl
  52       - spi_flash_ctrl.vhdl
  53     file_type : vhdlSource-2008
  54
  55   fpga:
  56     files:
  57       - fpga/main_bram.vhdl
  58       - fpga/soc_reset.vhdl
  59       - fpga/pp_fifo.vhd
  60       - fpga/pp_soc_uart.vhd
  61       - fpga/pp_utilities.vhd
  62       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  63     file_type : vhdlSource-2008
  64
  65   xilinx_specific:
  66     files:
  67       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  68       - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
  69       - fpga/fpga-random.xdc : {file_type : xdc}
  70
  71   debug_xilinx:
  72     files:
  73       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  74
  75   debug_dummy:
  76     files:
  77       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  78
  79   nexys_a7:
  80     files:
  81       - fpga/nexys_a7.xdc : {file_type : xdc}
  82       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  83       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  84
  85   nexys_video:
  86     files:
  87       - fpga/nexys-video.xdc : {file_type : xdc}
  88       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  89       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  90
  91   acorn_cle_215:
  92     files:
  93       - fpga/acorn-cle-215.xdc : {file_type : xdc}
  94       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  95       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
  96
  97   genesys2:
  98     files:
  99       - fpga/genesys2.xdc : {file_type : xdc}
 100       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 101       - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
 102
 103   arty_a7:
 104     files:
 105       - fpga/arty_a7.xdc : {file_type : xdc}
 106       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 107       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 108
 109   cmod_a7-35:
 110     files:
 111       - fpga/cmod_a7-35.xdc : {file_type : xdc}
 112       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 113       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 114
 115   litedram:
 116       depend : [":microwatt:litedram"]
 117
 118   liteeth:
 119       depend : [":microwatt:liteeth"]
 120
 121   uart16550:
 122       depend : ["::uart16550"]
 123
 124 targets:
 125   nexys_a7:
 126     default_tool: vivado
 127     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 128     parameters :
 129       - memory_size
 130       - ram_init_file
 131       - clk_input
 132       - clk_frequency
 133       - disable_flatten_core
 134       - log_length=2048
 135       - uart_is_16550
 136       - has_fpu
 137       - has_btc
 138     tools:
 139       vivado: {part : xc7a100tcsg324-1}
 140     toplevel : toplevel
 141
 142   acorn-cle-215-nodram:
 143     default_tool: vivado
 144     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 145     parameters :
 146       - memory_size
 147       - ram_init_file
 148       - clk_input
 149       - clk_frequency
 150       - disable_flatten_core
 151       - spi_flash_offset=10485760
 152       - log_length=2048
 153       - uart_is_16550
 154     tools:
 155       vivado: {part : xc7a200tsbg484-2}
 156     toplevel : toplevel
 157
 158   genesys2-nodram:
 159     default_tool: vivado
 160     filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 161     parameters :
 162       - memory_size
 163       - ram_init_file
 164       - clk_frequency
 165       - use_litedram=false
 166       - no_bram=false
 167       - disable_flatten_core
 168       - spi_flash_offset=10485760
 169       - log_length=2048
 170       - uart_is_16550=false
 171     tools:
 172       vivado: {part : xc7k325tffg900-2}
 173     toplevel : toplevel
 174
 175   acorn-cle-215:
 176     default_tool: vivado
 177     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 178     parameters :
 179       - memory_size
 180       - ram_init_file
 181       - use_litedram=true
 182       - disable_flatten_core
 183       - no_bram
 184       - spi_flash_offset=10485760
 185       - log_length=2048
 186       - uart_is_16550
 187     generate: [litedram_acorn_cle_215]
 188     tools:
 189       vivado: {part : xc7a200tsbg484-2}
 190     toplevel : toplevel
 191
 192   genesys2:
 193     default_tool: vivado
 194     filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 195     parameters :
 196       - memory_size
 197       - ram_init_file
 198       - use_litedram=true
 199       - disable_flatten_core
 200       - no_bram
 201       - spi_flash_offset=10485760
 202       - log_length=2048
 203       - uart_is_16550=false
 204     generate: [litedram_genesys2]
 205     tools:
 206       vivado: {part : xc7k325tffg900-2}
 207     toplevel : toplevel
 208
 209   nexys_video-nodram:
 210     default_tool: vivado
 211     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 212     parameters :
 213       - memory_size
 214       - ram_init_file
 215       - clk_input
 216       - clk_frequency
 217       - disable_flatten_core
 218       - spi_flash_offset=10485760
 219       - log_length=2048
 220       - uart_is_16550
 221       - has_fpu
 222       - has_btc
 223     tools:
 224       vivado: {part : xc7a200tsbg484-1}
 225     toplevel : toplevel
 226
 227   nexys_video:
 228     default_tool: vivado
 229     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 230     parameters:
 231       - memory_size
 232       - ram_init_file
 233       - use_litedram=true
 234       - disable_flatten_core
 235       - no_bram
 236       - spi_flash_offset=10485760
 237       - log_length=2048
 238       - uart_is_16550
 239       - has_fpu
 240       - has_btc
 241     generate: [litedram_nexys_video]
 242     tools:
 243       vivado: {part : xc7a200tsbg484-1}
 244     toplevel : toplevel
 245
 246   arty_a7-35-nodram:
 247     default_tool: vivado
 248     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 249     parameters :
 250       - memory_size
 251       - ram_init_file
 252       - clk_input
 253       - clk_frequency
 254       - disable_flatten_core
 255       - spi_flash_offset=3145728
 256       - log_length=512
 257       - uart_is_16550
 258       - has_uart1
 259       - has_fpu=false
 260       - has_btc=false
 261     tools:
 262       vivado: {part : xc7a35ticsg324-1L}
 263     toplevel : toplevel
 264
 265   arty_a7-35:
 266     default_tool: vivado
 267     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 268     parameters :
 269       - memory_size
 270       - ram_init_file
 271       - use_litedram=true
 272       - use_liteeth=true
 273       - disable_flatten_core
 274       - no_bram
 275       - spi_flash_offset=3145728
 276       - log_length=512
 277       - uart_is_16550
 278       - has_uart1
 279       - has_fpu=false
 280       - has_btc=false
 281     generate: [litedram_arty, liteeth_arty]
 282     tools:
 283       vivado: {part : xc7a35ticsg324-1L}
 284     toplevel : toplevel
 285
 286   arty_a7-100-nodram:
 287     default_tool: vivado
 288     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 289     parameters :
 290       - memory_size
 291       - ram_init_file
 292       - clk_input
 293       - clk_frequency
 294       - disable_flatten_core
 295       - spi_flash_offset=4194304
 296       - log_length=2048
 297       - uart_is_16550
 298       - has_uart1
 299       - has_fpu
 300       - has_btc
 301     tools:
 302       vivado: {part : xc7a100ticsg324-1L}
 303     toplevel : toplevel
 304
 305   arty_a7-100:
 306     default_tool: vivado
 307     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
 308     parameters:
 309       - memory_size
 310       - ram_init_file
 311       - use_litedram=true
 312       - use_liteeth=true
 313       - disable_flatten_core
 314       - no_bram
 315       - spi_flash_offset=4194304
 316       - log_length=2048
 317       - uart_is_16550
 318       - has_uart1
 319       - has_fpu
 320       - has_btc
 321     generate: [litedram_arty, liteeth_arty]
 322     tools:
 323       vivado: {part : xc7a100ticsg324-1L}
 324     toplevel : toplevel
 325
 326   cmod_a7-35:
 327     default_tool: vivado
 328     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 329     parameters :
 330       - memory_size
 331       - ram_init_file
 332       - reset_low=false
 333       - clk_input=12000000
 334       - clk_frequency
 335       - disable_flatten_core
 336       - log_length=512
 337       - uart_is_16550
 338       - has_fpu=false
 339       - has_btc=false
 340     tools:
 341       vivado: {part : xc7a35tcpg236-1}
 342     toplevel : toplevel
 343
 344   synth:
 345     filesets: [core, soc, xilinx_specific]
 346     tools:
 347       vivado: {pnr : none}
 348     toplevel: core
 349
 350 generate:
 351   litedram_arty:
 352     generator: litedram_gen
 353     parameters: {board : arty}
 354
 355   liteeth_arty:
 356     generator: liteeth_gen
 357     parameters: {board : arty}
 358
 359   litedram_nexys_video:
 360     generator: litedram_gen
 361     parameters: {board : nexys-video}
 362
 363   litedram_acorn_cle_215:
 364     generator: litedram_gen
 365     parameters: {board : acorn-cle-215}
 366
 367   litedram_genesys2:
 368     generator: litedram_gen
 369     parameters: {board : genesys2}
 370
 371 parameters:
 372   memory_size:
 373     datatype    : int
 374     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 375     paramtype   : generic
 376     default     : 16384
 377
 378   ram_init_file:
 379     datatype    : file
 380     description : Initial on-chip RAM contents
 381     paramtype   : generic
 382
 383   reset_low:
 384     datatype    : bool
 385     description : External reset button polarity
 386     paramtype   : generic
 387
 388   clk_input:
 389     datatype    : int
 390     description : Clock input frequency in HZ (for top-generic based boards)
 391     paramtype   : generic
 392     default     : 100000000
 393
 394   clk_frequency:
 395     datatype    : int
 396     description : Generated system clock frequency in HZ (for top-generic based boards)
 397     paramtype   : generic
 398     default     : 100000000
 399
 400   has_fpu:
 401     datatype    : bool
 402     description : Include a floating-point unit in the core
 403     paramtype   : generic
 404     default     : true
 405
 406   has_btc:
 407     datatype    : bool
 408     description : Include a branch target cache in the core
 409     paramtype   : generic
 410     default     : true
 411
 412   disable_flatten_core:
 413     datatype    : bool
 414     description : Prevent Vivado from flattening the main core components
 415     paramtype   : generic
 416     default     : false
 417
 418   use_litedram:
 419     datatype    : bool
 420     description : Use liteDRAM
 421     paramtype   : generic
 422     default     : false
 423
 424   use_liteeth:
 425     datatype    : bool
 426     description : Use liteEth
 427     paramtype   : generic
 428     default     : false
 429
 430   uart_is_16550:
 431     datatype    : bool
 432     description : Use 16550-compatible UART from OpenCores
 433     paramtype   : generic
 434     default     : true
 435
 436   has_uart1:
 437     datatype    : bool
 438     description : Enable second UART (always 16550-compatible)
 439     paramtype   : generic
 440     default     : false
 441
 442   no_bram:
 443     datatype    : bool
 444     description : No internal block RAM (only DRAM and init code carrying payload)
 445     paramtype   : generic
 446     default     : false
 447
 448   spi_flash_offset:
 449     datatype    : int
 450     description : Offset (in bytes) in the SPI flash of the code payload to run
 451     paramtype   : generic
 452
 453   log_length:
 454     datatype    : int
 455     description : Length of the core log buffer in entries (32 bytes each)
 456     paramtype   : generic