microwatt.core

   1 CAPI=2:
   2
   3 name : ::microwatt:0
   4
   5 filesets:
   6   core:
   7     files:
   8       - decode_types.vhdl
   9       - wishbone_types.vhdl
  10       - common.vhdl
  11       - fetch1.vhdl
  12       - decode1.vhdl
  13       - helpers.vhdl
  14       - decode2.vhdl
  15       - register_file.vhdl
  16       - cr_file.vhdl
  17       - crhelpers.vhdl
  18       - ppc_fx_insns.vhdl
  19       - sim_console.vhdl
  20       - logical.vhdl
  21       - countbits.vhdl
  22       - control.vhdl
  23       - execute1.vhdl
  24       - fpu.vhdl
  25       - loadstore1.vhdl
  26       - mmu.vhdl
  27       - dcache.vhdl
  28       - divider.vhdl
  29       - rotator.vhdl
  30       - pmu.vhdl
  31       - writeback.vhdl
  32       - insn_helpers.vhdl
  33       - core.vhdl
  34       - icache.vhdl
  35       - plru.vhdl
  36       - cache_ram.vhdl
  37       - core_debug.vhdl
  38       - utils.vhdl
  39     file_type : vhdlSource-2008
  40
  41   soc:
  42     files:
  43       - wishbone_arbiter.vhdl
  44       - wishbone_debug_master.vhdl
  45       - wishbone_bram_wrapper.vhdl
  46       - soc.vhdl
  47       - xics.vhdl
  48       - gpio.vhdl
  49       - syscon.vhdl
  50       - sync_fifo.vhdl
  51       - spi_rxtx.vhdl
  52       - spi_flash_ctrl.vhdl
  53     file_type : vhdlSource-2008
  54
  55   fpga:
  56     files:
  57       - fpga/main_bram.vhdl
  58       - fpga/soc_reset.vhdl
  59       - fpga/pp_fifo.vhd
  60       - fpga/pp_soc_uart.vhd
  61       - fpga/pp_utilities.vhd
  62       - fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
  63     file_type : vhdlSource-2008
  64
  65   xilinx_specific:
  66     files:
  67       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
  68       - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
  69       - fpga/fpga-random.xdc : {file_type : xdc}
  70
  71   debug_xilinx:
  72     files:
  73       - dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
  74
  75   debug_dummy:
  76     files:
  77       - dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
  78
  79   nexys_a7:
  80     files:
  81       - fpga/nexys_a7.xdc : {file_type : xdc}
  82       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  83       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
  84
  85   nexys_video:
  86     files:
  87       - fpga/nexys-video.xdc : {file_type : xdc}
  88       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  89       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
  90
  91   acorn_cle_215:
  92     files:
  93       - fpga/acorn-cle-215.xdc : {file_type : xdc}
  94       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
  95       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
  96
  97   genesys2:
  98     files:
  99       - fpga/genesys2.xdc : {file_type : xdc}
 100       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 101       - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
 102
 103   arty_a7:
 104     files:
 105       - fpga/arty_a7.xdc : {file_type : xdc}
 106       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 107       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 108
 109   wukong-v2:
 110     files:
 111       - fpga/wukong-v2.xdc : {file_type : xdc}
 112       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
 113       - fpga/top-wukong-v2.vhdl : {file_type : vhdlSource-2008}
 114
 115   cmod_a7-35:
 116     files:
 117       - fpga/cmod_a7-35.xdc : {file_type : xdc}
 118       - fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
 119       - fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
 120
 121   litedram:
 122       depend : [":microwatt:litedram"]
 123
 124   liteeth:
 125       depend : [":microwatt:liteeth"]
 126
 127   litesdcard:
 128       depend : [":microwatt:litesdcard"]
 129
 130   uart16550:
 131       depend : ["::uart16550"]
 132
 133 targets:
 134   nexys_a7:
 135     default_tool: vivado
 136     filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 137     parameters :
 138       - memory_size
 139       - ram_init_file
 140       - clk_input
 141       - clk_frequency
 142       - disable_flatten_core
 143       - log_length=2048
 144       - uart_is_16550
 145       - has_fpu
 146       - has_btc
 147       - has_short_mult
 148     tools:
 149       vivado: {part : xc7a100tcsg324-1}
 150     toplevel : toplevel
 151
 152   acorn-cle-215-nodram:
 153     default_tool: vivado
 154     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 155     parameters :
 156       - memory_size
 157       - ram_init_file
 158       - clk_input
 159       - clk_frequency
 160       - disable_flatten_core
 161       - spi_flash_offset=10485760
 162       - log_length=2048
 163       - uart_is_16550
 164     tools:
 165       vivado: {part : xc7a200tsbg484-2}
 166     toplevel : toplevel
 167
 168   genesys2-nodram:
 169     default_tool: vivado
 170     filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 171     parameters :
 172       - memory_size
 173       - ram_init_file
 174       - clk_frequency
 175       - use_litedram=false
 176       - no_bram=false
 177       - disable_flatten_core
 178       - spi_flash_offset=10485760
 179       - log_length=2048
 180       - uart_is_16550=false
 181     tools:
 182       vivado: {part : xc7k325tffg900-2}
 183     toplevel : toplevel
 184
 185   acorn-cle-215:
 186     default_tool: vivado
 187     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 188     parameters :
 189       - memory_size
 190       - ram_init_file
 191       - use_litedram=true
 192       - disable_flatten_core
 193       - no_bram
 194       - spi_flash_offset=10485760
 195       - log_length=2048
 196       - uart_is_16550
 197     generate: [litedram_acorn_cle_215]
 198     tools:
 199       vivado: {part : xc7a200tsbg484-2}
 200     toplevel : toplevel
 201
 202   genesys2:
 203     default_tool: vivado
 204     filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
 205     parameters :
 206       - memory_size
 207       - ram_init_file
 208       - use_litedram=true
 209       - disable_flatten_core
 210       - no_bram
 211       - spi_flash_offset=10485760
 212       - log_length=2048
 213       - uart_is_16550=false
 214     generate: [litedram_genesys2]
 215     tools:
 216       vivado: {part : xc7k325tffg900-2}
 217     toplevel : toplevel
 218
 219   nexys_video-nodram:
 220     default_tool: vivado
 221     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 222     parameters :
 223       - memory_size
 224       - ram_init_file
 225       - clk_input
 226       - clk_frequency
 227       - disable_flatten_core
 228       - spi_flash_offset=10485760
 229       - log_length=2048
 230       - uart_is_16550
 231       - has_fpu
 232       - has_btc
 233     tools:
 234       vivado: {part : xc7a200tsbg484-1}
 235     toplevel : toplevel
 236
 237   nexys_video:
 238     default_tool: vivado
 239     filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
 240     parameters:
 241       - memory_size
 242       - ram_init_file
 243       - use_litedram=true
 244       - use_liteeth=true
 245       - use_litesdcard=true
 246       - disable_flatten_core
 247       - no_bram
 248       - spi_flash_offset=10485760
 249       - log_length=2048
 250       - uart_is_16550
 251       - has_fpu
 252       - has_btc
 253       - has_short_mult
 254     generate: [litedram_nexys_video, liteeth_nexys_video, litesdcard_nexys_video]
 255     tools:
 256       vivado: {part : xc7a200tsbg484-1}
 257     toplevel : toplevel
 258
 259   arty_a7-35-nodram:
 260     default_tool: vivado
 261     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
 262     parameters :
 263       - memory_size
 264       - ram_init_file
 265       - clk_input
 266       - clk_frequency
 267       - disable_flatten_core
 268       - spi_flash_offset=3145728
 269       - log_length=512
 270       - uart_is_16550
 271       - has_uart1
 272       - has_fpu=false
 273       - has_btc=false
 274       - has_short_mult
 275       - use_litesdcard
 276     tools:
 277       vivado: {part : xc7a35ticsg324-1L}
 278     toplevel : toplevel
 279
 280   arty_a7-35:
 281     default_tool: vivado
 282     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
 283     parameters :
 284       - memory_size
 285       - ram_init_file
 286       - use_litedram=true
 287       - use_liteeth=true
 288       - use_litesdcard
 289       - disable_flatten_core
 290       - no_bram
 291       - spi_flash_offset=3145728
 292       - log_length=512
 293       - uart_is_16550
 294       - has_uart1
 295       - has_fpu=false
 296       - has_btc=false
 297       - has_short_mult
 298     generate: [litedram_arty, liteeth_arty, litesdcard_arty]
 299     tools:
 300       vivado: {part : xc7a35ticsg324-1L}
 301     toplevel : toplevel
 302
 303   arty_a7-100-nodram:
 304     default_tool: vivado
 305     filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
 306     parameters :
 307       - memory_size
 308       - ram_init_file
 309       - clk_input
 310       - clk_frequency
 311       - disable_flatten_core
 312       - spi_flash_offset=4194304
 313       - log_length=2048
 314       - uart_is_16550
 315       - has_uart1
 316       - has_fpu
 317       - has_btc
 318       - has_short_mult
 319       - use_litesdcard
 320     tools:
 321       vivado: {part : xc7a100ticsg324-1L}
 322     toplevel : toplevel
 323
 324   arty_a7-100:
 325     default_tool: vivado
 326     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
 327     parameters:
 328       - memory_size
 329       - ram_init_file
 330       - use_litedram=true
 331       - use_liteeth=true
 332       - use_litesdcard
 333       - disable_flatten_core
 334       - no_bram
 335       - spi_flash_offset=4194304
 336       - log_length=2048
 337       - uart_is_16550
 338       - has_uart1
 339       - has_fpu
 340       - has_btc
 341       - has_short_mult
 342     generate: [litedram_arty, liteeth_arty, litesdcard_arty]
 343     tools:
 344       vivado: {part : xc7a100ticsg324-1L}
 345     toplevel : toplevel
 346
 347   wukong-v2-a100t-nodram:
 348     default_tool: vivado
 349     filesets: [core, wukong-v2, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
 350     parameters:
 351       - memory_size
 352       - ram_init_file
 353       - use_litedram=false
 354       - use_liteeth=false
 355       - use_litesdcard=true
 356       - disable_flatten_core
 357       - spi_flash_offset=4194304
 358       - clk_frequency=100000000
 359       - log_length=2048
 360       - uart_is_16550
 361       - has_fpu
 362       - has_btc
 363       - has_short_mult
 364     generate: [litesdcard_wukong-v2]
 365     tools:
 366       vivado: {part : xc7a100tfgg676-1}
 367     toplevel : toplevel
 368
 369   wukong-v2-a100t:
 370     default_tool: vivado
 371     filesets: [core, wukong-v2, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
 372     parameters:
 373       - memory_size=0
 374       - ram_init_file
 375       - use_litedram=true
 376       - use_liteeth=true
 377       - use_litesdcard=true
 378       - disable_flatten_core
 379       - no_bram=true
 380       - spi_flash_offset=4194304
 381       - log_length=0
 382       - uart_is_16550
 383       - has_fpu
 384       - has_btc
 385       - has_short_mult
 386     generate: [litedram_wukong-v2, liteeth_wukong-v2, litesdcard_wukong-v2]
 387     tools:
 388       vivado: {part : xc7a100tfgg676-1}
 389     toplevel : toplevel
 390
 391   cmod_a7-35:
 392     default_tool: vivado
 393     filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
 394     parameters :
 395       - memory_size
 396       - ram_init_file
 397       - reset_low=false
 398       - clk_input=12000000
 399       - clk_frequency
 400       - disable_flatten_core
 401       - log_length=512
 402       - uart_is_16550
 403       - has_fpu=false
 404       - has_btc=false
 405     tools:
 406       vivado: {part : xc7a35tcpg236-1}
 407     toplevel : toplevel
 408
 409   synth:
 410     filesets: [core, soc, xilinx_specific]
 411     tools:
 412       vivado: {pnr : none}
 413     toplevel: core
 414
 415 generate:
 416   litedram_arty:
 417     generator: litedram_gen
 418     parameters: {board : arty}
 419
 420   liteeth_arty:
 421     generator: liteeth_gen
 422     parameters: {board : arty}
 423
 424   litesdcard_arty:
 425     generator: litesdcard_gen
 426     parameters: {vendor : xilinx}
 427
 428   litesdcard_nexys_video:
 429     generator: litesdcard_gen
 430     parameters: {vendor : xilinx}
 431
 432   litedram_nexys_video:
 433     generator: litedram_gen
 434     parameters: {board : nexys-video}
 435
 436   liteeth_nexys_video:
 437     generator: liteeth_gen
 438     parameters: {board : nexys-video}
 439
 440   litedram_acorn_cle_215:
 441     generator: litedram_gen
 442     parameters: {board : acorn-cle-215}
 443
 444   litedram_genesys2:
 445     generator: litedram_gen
 446     parameters: {board : genesys2}
 447
 448   litedram_wukong-v2:
 449     generator: litedram_gen
 450     parameters: {board : wukong-v2}
 451
 452   liteeth_wukong-v2:
 453     generator: liteeth_gen
 454     parameters: {board : wukong-v2}
 455
 456   litesdcard_wukong-v2:
 457     generator: litesdcard_gen
 458     parameters: {vendor : xilinx}
 459
 460 parameters:
 461   memory_size:
 462     datatype    : int
 463     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
 464     paramtype   : generic
 465     default     : 16384
 466
 467   ram_init_file:
 468     datatype    : file
 469     description : Initial on-chip RAM contents
 470     paramtype   : generic
 471
 472   reset_low:
 473     datatype    : bool
 474     description : External reset button polarity
 475     paramtype   : generic
 476
 477   clk_input:
 478     datatype    : int
 479     description : Clock input frequency in HZ (for top-generic based boards)
 480     paramtype   : generic
 481     default     : 100000000
 482
 483   clk_frequency:
 484     datatype    : int
 485     description : Generated system clock frequency in HZ (for top-generic based boards)
 486     paramtype   : generic
 487     default     : 100000000
 488
 489   has_fpu:
 490     datatype    : bool
 491     description : Include a floating-point unit in the core
 492     paramtype   : generic
 493     default     : true
 494
 495   has_btc:
 496     datatype    : bool
 497     description : Include a branch target cache in the core
 498     paramtype   : generic
 499     default     : true
 500
 501   has_short_mult:
 502     datatype    : bool
 503     description : Include a 16 bit x 16 bit single-cycle multiplier in the core
 504     paramtype   : generic
 505     default     : false
 506
 507   disable_flatten_core:
 508     datatype    : bool
 509     description : Prevent Vivado from flattening the main core components
 510     paramtype   : generic
 511     default     : false
 512
 513   use_litedram:
 514     datatype    : bool
 515     description : Use liteDRAM
 516     paramtype   : generic
 517     default     : false
 518
 519   use_liteeth:
 520     datatype    : bool
 521     description : Use liteEth
 522     paramtype   : generic
 523     default     : false
 524
 525   use_litesdcard:
 526     datatype    : bool
 527     description : Use LiteSDCard
 528     paramtype   : generic
 529     default     : false
 530
 531   uart_is_16550:
 532     datatype    : bool
 533     description : Use 16550-compatible UART from OpenCores
 534     paramtype   : generic
 535     default     : true
 536
 537   has_uart1:
 538     datatype    : bool
 539     description : Enable second UART (always 16550-compatible)
 540     paramtype   : generic
 541     default     : false
 542
 543   no_bram:
 544     datatype    : bool
 545     description : No internal block RAM (only DRAM and init code carrying payload)
 546     paramtype   : generic
 547     default     : false
 548
 549   spi_flash_offset:
 550     datatype    : int
 551     description : Offset (in bytes) in the SPI flash of the code payload to run
 552     paramtype   : generic
 553
 554   log_length:
 555     datatype    : int
 556     description : Length of the core log buffer in entries (32 bytes each)
 557     paramtype   : generic