misc/yosys.proto

   1 //
   2 // yosys -- Yosys Open SYnthesis Suite
   3 //
   4 // Copyright (C) 2018  Serge Bazanski <q3k@symbioticeda.com>
   5 //
   6 // Permission to use, copy, modify, and/or distribute this software for any
   7 // purpose with or without fee is hereby granted, provided that the above
   8 // copyright notice and this permission notice appear in all copies.
   9 //
  10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17 //
  18
  19 /// Protobuf definition of Yosys RTLIL dump/restore format for RTL designs.
  20
  21 syntax = "proto3";
  22
  23 package yosys.pb;
  24
  25 // Port direction.
  26 enum Direction {
  27     DIRECTION_INVALID = 0;
  28     DIRECTION_INPUT = 1;
  29     DIRECTION_OUTPUT = 2;
  30     DIRECTION_INOUT = 3;
  31 }
  32
  33 // A freeform parameter/attribute value.
  34 message Parameter {
  35     oneof value {
  36         int64 int = 1;
  37         string str = 2;
  38     }
  39 }
  40
  41 // A signal in the design - either a unique identifier for one, or a constant
  42 // driver (low or high).
  43 message Signal {
  44     // A constant signal driver in the design.
  45     enum ConstantDriver {
  46         CONSTANT_DRIVER_INVALID = 0;
  47         CONSTANT_DRIVER_LOW = 1;
  48         CONSTANT_DRIVER_HIGH = 2;
  49         CONSTANT_DRIVER_Z = 3;
  50         CONSTANT_DRIVER_X = 4;
  51     }
  52     oneof type {
  53         // Signal uniquely identified by ID number.
  54         int64 id = 1;
  55         // Constant driver.
  56         ConstantDriver constant = 2;
  57     }
  58 }
  59
  60 // A vector of signals.
  61 message BitVector {
  62     repeated Signal signal = 1;
  63 }
  64
  65 // A netlist module.
  66 message Module {
  67     // Freeform attributes.
  68     map<string, Parameter> attribute = 1;
  69
  70     // Named ports in this module.
  71     message Port {
  72         Direction direction = 1;
  73         BitVector bits = 2;
  74     }
  75     map<string, Port> port = 2;
  76
  77     // Named cells in this module.
  78     message Cell {
  79         // Set to true when the name of this cell is automatically created and
  80         // likely not of interest for a regular user.
  81         bool hide_name = 1;
  82         string type = 2;
  83         // Set if this module has an AIG model available.
  84         string model = 3;
  85         // Freeform parameters.
  86         map<string, Parameter> parameter = 4;
  87         // Freeform attributes.
  88         map<string, Parameter> attribute = 5;
  89
  90         /// Ports of the cell.
  91         // Direction of the port, if interface is known.
  92         map<string, Direction> port_direction = 6;
  93         // Connection of named port to signal(s).
  94         map<string, BitVector> connection = 7;
  95     }
  96     map<string, Cell> cell = 3;
  97
  98     // Nets in this module.
  99     message Netname {
 100         // Set to true when the name of this net is automatically created and
 101         // likely not of interest for a regular user.
 102         bool hide_name = 1;
 103         // Signal(s) that make up this net.
 104         BitVector bits = 2;
 105         // Freeform attributes.
 106         map<string, Parameter> attributes = 3;
 107     }
 108     repeated Netname netname = 4;
 109 }
 110
 111 // And-Inverter-Graph model.
 112 message Model {
 113     message Node {
 114         // Type of AIG node - or, what its' value is.
 115         enum Type {
 116             TYPE_INVALID = 0;
 117             // The node's value is the value of the specified input port bit.
 118             TYPE_PORT = 1;
 119             // The node's value is the inverted value of the specified input
 120             // port bit.
 121             TYPE_NPORT = 2;
 122             // The node's value is the ANDed value of specified nodes.
 123             TYPE_AND = 3;
 124             // The node's value is the NANDed value of specified nodes.
 125             TYPE_NAND = 4;
 126             // The node's value is a constant 1.
 127             TYPE_TRUE = 5;
 128             // The node's value is a constant 0.
 129             TYPE_FALSE = 6;
 130         };
 131         Type type = 1;
 132
 133         message Port {
 134             // Name of port.
 135             string portname = 1;
 136             // Bit index in port.
 137             int64 bitindex = 2;
 138         }
 139         message Gate {
 140             // Node index of left side of operation.
 141             int64 left = 1;
 142             // Node index of right side of operation.
 143             int64 right = 2;
 144         }
 145         oneof node {
 146             // Set for PORT, NPORT
 147             Port port = 2;
 148             // Set for AND, NAND.
 149             Gate gate = 3;
 150         }
 151
 152         // Set when the node drives given output port(s).
 153         message OutPort {
 154             // Name of port.
 155             string name = 1;
 156             // Bit index in port.
 157             int64 bit_index = 2;
 158         }
 159         repeated OutPort out_port = 4;
 160     }
 161
 162     // List of  AIG nodes - each is explicitely numbered by its' index in this
 163     // array.
 164     repeated Node node = 1;
 165 }
 166
 167 // A Yosys design netlist dumped from RTLIL.
 168 message Design {
 169     // Human-readable freeform 'remark' string.
 170     string creator = 1;
 171     // List of named modules in design.
 172     map<string, Module> modules = 2;
 173     // List of named AIG models in design (if AIG export enabled).
 174     map<string, Model> models = 3;
 175 }