43e91b679018142f3e063a593d5baf42dce9b9cc
[ecpprog.git] / mpsse.c
1 /*
2 * iceprog -- simple programming tool for FTDI-based Lattice iCE programmers
3 *
4 * Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2018 Piotr Esden-Tempski <piotr@esden.net>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * Relevant Documents:
20 * -------------------
21 * http://www.ftdichip.com/Support/Documents/AppNotes/AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf
22 */
23
24 #define _GNU_SOURCE
25
26 #include <ftdi.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <stdbool.h>
30 #include <stdlib.h>
31 #include <unistd.h>
32
33 #include "mpsse.h"
34
35 // ---------------------------------------------------------
36 // MPSSE / FTDI definitions
37 // ---------------------------------------------------------
38
39 /* FTDI bank pinout typically used for iCE dev boards
40 * BUS IO | Signal | Control
41 * -------+--------+--------------
42 * xDBUS0 | SCK | MPSSE
43 * xDBUS1 | MOSI | MPSSE
44 * xDBUS2 | MISO | MPSSE
45 * xDBUS3 | nc |
46 * xDBUS4 | CS | GPIO
47 * xDBUS5 | nc |
48 * xDBUS6 | CDONE | GPIO
49 * xDBUS7 | CRESET | GPIO
50 */
51
52 struct ftdi_context mpsse_ftdic;
53 bool mpsse_ftdic_open = false;
54 bool mpsse_ftdic_latency_set = false;
55 unsigned char mpsse_ftdi_latency;
56
57
58 // ---------------------------------------------------------
59 // MPSSE / FTDI function implementations
60 // ---------------------------------------------------------
61
62 void mpsse_check_rx()
63 {
64 uint8_t cnt = 0;
65 while (1) {
66 uint8_t data;
67 int rc = ftdi_read_data(&mpsse_ftdic, &data, 1);
68 if (rc <= 0)
69 break;
70 fprintf(stderr, "unexpected rx byte: %02X\n", data);
71 cnt++;
72
73 if(cnt > 32)
74 break;
75 }
76 }
77
78 void mpsse_error(int status)
79 {
80 mpsse_check_rx();
81 fprintf(stderr, "ABORT.\n");
82 if (mpsse_ftdic_open) {
83 if (mpsse_ftdic_latency_set)
84 ftdi_set_latency_timer(&mpsse_ftdic, mpsse_ftdi_latency);
85 ftdi_usb_close(&mpsse_ftdic);
86 }
87 ftdi_deinit(&mpsse_ftdic);
88 exit(status);
89 }
90
91 uint8_t mpsse_recv_byte()
92 {
93 uint8_t data;
94 while (1) {
95 int rc = ftdi_read_data(&mpsse_ftdic, &data, 1);
96 if (rc < 0) {
97 fprintf(stderr, "Read error.\n");
98 mpsse_error(2);
99 }
100 if (rc == 1)
101 break;
102 usleep(100);
103 }
104 return data;
105 }
106
107 void mpsse_send_byte(uint8_t data)
108 {
109 int rc = ftdi_write_data(&mpsse_ftdic, &data, 1);
110 if (rc != 1) {
111 fprintf(stderr, "Write error (single byte, rc=%d, expected %d)(%s).\n", rc, 1, ftdi_get_error_string(&mpsse_ftdic));
112 mpsse_error(2);
113 }
114 }
115
116 void mpsse_purge(void){
117 int rc = ftdi_usb_purge_buffers(&mpsse_ftdic);
118 if (rc != 0) {
119 fprintf(stderr, "Purge error.\n");
120 mpsse_error(2);
121 }
122 }
123
124 void mpsse_send_spi(uint8_t *data, int n)
125 {
126 if (n < 1)
127 return;
128
129 /* Output only, update data on negative clock edge. */
130 mpsse_send_byte(MC_DATA_OUT | MC_DATA_OCN);
131 mpsse_send_byte(n - 1);
132 mpsse_send_byte((n - 1) >> 8);
133
134 int rc = ftdi_write_data(&mpsse_ftdic, data, n);
135 if (rc != n) {
136 fprintf(stderr, "Write error (chunk, rc=%d, expected %d).\n", rc, n);
137 mpsse_error(2);
138 }
139 }
140
141 void mpsse_xfer_spi(uint8_t *data, int n)
142 {
143 if (n < 1)
144 return;
145
146 /* Input and output, update data on negative edge read on positive. */
147 mpsse_send_byte(MC_DATA_IN | MC_DATA_OUT | MC_DATA_OCN);
148 mpsse_send_byte(n - 1);
149 mpsse_send_byte((n - 1) >> 8);
150
151 int rc = ftdi_write_data(&mpsse_ftdic, data, n);
152 if (rc != n) {
153 fprintf(stderr, "Write error (chunk, rc=%d, expected %d).\n", rc, n);
154 mpsse_error(2);
155 }
156
157 for (int i = 0; i < n; i++)
158 data[i] = mpsse_recv_byte();
159 }
160
161 uint8_t mpsse_xfer_spi_bits(uint8_t data, int n)
162 {
163 if (n < 1)
164 return 0;
165
166 /* Input and output, update data on negative edge read on positive, bits. */
167 mpsse_send_byte(MC_DATA_IN | MC_DATA_OUT | MC_DATA_OCN | MC_DATA_BITS);
168 mpsse_send_byte(n - 1);
169 mpsse_send_byte(data);
170
171 return mpsse_recv_byte();
172 }
173
174 void mpsse_set_gpio(uint8_t gpio, uint8_t direction)
175 {
176 mpsse_send_byte(MC_SETB_LOW);
177 mpsse_send_byte(gpio); /* Value */
178 mpsse_send_byte(direction); /* Direction */
179 }
180
181 int mpsse_readb_low(void)
182 {
183 uint8_t data;
184 mpsse_send_byte(MC_READB_LOW);
185 data = mpsse_recv_byte();
186 return data;
187 }
188
189 int mpsse_readb_high(void)
190 {
191 uint8_t data;
192 mpsse_send_byte(MC_READB_HIGH);
193 data = mpsse_recv_byte();
194 return data;
195 }
196
197 void mpsse_send_dummy_bytes(uint8_t n)
198 {
199 // add 8 x count dummy bits (aka n bytes)
200 mpsse_send_byte(MC_CLK_N8);
201 mpsse_send_byte(n - 1);
202 mpsse_send_byte(0x00);
203
204 }
205
206 void mpsse_send_dummy_bit(void)
207 {
208 // add 1 dummy bit
209 mpsse_send_byte(MC_CLK_N);
210 mpsse_send_byte(0x00);
211 }
212
213 void mpsse_jtag_init(){
214 mpsse_send_byte(MC_SETB_LOW);
215 mpsse_send_byte(0x08); /* Value */
216 mpsse_send_byte(0x0B); /* Direction */
217
218 /* Reset JTAG State machine */
219 jtag_init();
220 }
221
222 void mpsse_jtag_tms(uint8_t bits, uint8_t pattern){
223 mpsse_send_byte(MC_DATA_TMS | MC_DATA_LSB | MC_DATA_BITS);
224 mpsse_send_byte(bits-1);
225 mpsse_send_byte(pattern);
226 }
227
228 void mpsse_init(int ifnum, const char *devstr, bool slow_clock)
229 {
230 enum ftdi_interface ftdi_ifnum = INTERFACE_A;
231
232 switch (ifnum) {
233 case 0:
234 ftdi_ifnum = INTERFACE_A;
235 break;
236 case 1:
237 ftdi_ifnum = INTERFACE_B;
238 break;
239 case 2:
240 ftdi_ifnum = INTERFACE_C;
241 break;
242 case 3:
243 ftdi_ifnum = INTERFACE_D;
244 break;
245 default:
246 ftdi_ifnum = INTERFACE_A;
247 break;
248 }
249
250 ftdi_init(&mpsse_ftdic);
251 ftdi_set_interface(&mpsse_ftdic, ftdi_ifnum);
252
253 if (devstr != NULL) {
254 if (ftdi_usb_open_string(&mpsse_ftdic, devstr)) {
255 fprintf(stderr, "Can't find iCE FTDI USB device (device string %s).\n", devstr);
256 mpsse_error(2);
257 }
258 } else {
259 if (ftdi_usb_open(&mpsse_ftdic, 0x0403, 0x6010) && ftdi_usb_open(&mpsse_ftdic, 0x0403, 0x6014)) {
260 fprintf(stderr, "Can't find iCE FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).\n");
261 mpsse_error(2);
262 }
263 }
264
265 mpsse_ftdic_open = true;
266
267 if (ftdi_usb_reset(&mpsse_ftdic)) {
268 fprintf(stderr, "Failed to reset iCE FTDI USB device.\n");
269 mpsse_error(2);
270 }
271
272 if (ftdi_usb_purge_buffers(&mpsse_ftdic)) {
273 fprintf(stderr, "Failed to purge buffers on iCE FTDI USB device.\n");
274 mpsse_error(2);
275 }
276
277 if (ftdi_get_latency_timer(&mpsse_ftdic, &mpsse_ftdi_latency) < 0) {
278 fprintf(stderr, "Failed to get latency timer (%s).\n", ftdi_get_error_string(&mpsse_ftdic));
279 mpsse_error(2);
280 }
281
282 /* 1 is the fastest polling, it means 1 kHz polling */
283 if (ftdi_set_latency_timer(&mpsse_ftdic, 1) < 0) {
284 fprintf(stderr, "Failed to set latency timer (%s).\n", ftdi_get_error_string(&mpsse_ftdic));
285 mpsse_error(2);
286 }
287
288 mpsse_ftdic_latency_set = true;
289
290 /* Enter MPSSE (Multi-Protocol Synchronous Serial Engine) mode. Set all pins to output. */
291 if (ftdi_set_bitmode(&mpsse_ftdic, 0xff, BITMODE_MPSSE) < 0) {
292 fprintf(stderr, "Failed to set BITMODE_MPSSE on FTDI USB device.\n");
293 mpsse_error(2);
294 }
295
296 int rc = ftdi_usb_purge_buffers(&mpsse_ftdic);
297 if (rc != 0) {
298 fprintf(stderr, "Purge error.\n");
299 mpsse_error(2);
300 }
301
302 // enable clock divide by 5
303 //mpsse_send_byte(MC_TCK_D5);
304
305 if (slow_clock) {
306 // set 50 kHz clock
307 mpsse_send_byte(MC_SET_CLK_DIV);
308 mpsse_send_byte(119);
309 mpsse_send_byte(0x00);
310 } else {
311 // set 6 MHz clock
312 mpsse_send_byte(MC_SET_CLK_DIV);
313 mpsse_send_byte(5);
314 mpsse_send_byte(0x00);
315 }
316
317 }
318
319 void mpsse_close(void)
320 {
321 ftdi_set_latency_timer(&mpsse_ftdic, mpsse_ftdi_latency);
322 ftdi_disable_bitbang(&mpsse_ftdic);
323 ftdi_usb_close(&mpsse_ftdic);
324 ftdi_deinit(&mpsse_ftdic);
325 }