mpsse.h

   1 /*
   2  *  iceprog -- simple programming tool for FTDI-based Lattice iCE programmers
   3  *
   4  *  Copyright (C) 2015  Clifford Wolf <clifford@clifford.at>
   5  *  Copyright (C) 2018  Piotr Esden-Tempski <piotr@esden.net>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #ifndef MPSSE_H
  21 #define MPSSE_H
  22
  23 #include <stdint.h>
  24
  25
  26
  27 /* MPSSE engine command definitions */
  28 enum mpsse_cmd
  29 {
  30         /* Mode commands */
  31         MC_SETB_LOW = 0x80, /* Set Data bits LowByte */
  32         MC_READB_LOW = 0x81, /* Read Data bits LowByte */
  33         MC_SETB_HIGH = 0x82, /* Set Data bits HighByte */
  34         MC_READB_HIGH = 0x83, /* Read data bits HighByte */
  35         MC_LOOPBACK_EN = 0x84, /* Enable loopback */
  36         MC_LOOPBACK_DIS = 0x85, /* Disable loopback */
  37         MC_SET_CLK_DIV = 0x86, /* Set clock divisor */
  38         MC_FLUSH = 0x87, /* Flush buffer fifos to the PC. */
  39         MC_WAIT_H = 0x88, /* Wait on GPIOL1 to go high. */
  40         MC_WAIT_L = 0x89, /* Wait on GPIOL1 to go low. */
  41         MC_TCK_X5 = 0x8A, /* Disable /5 div, enables 60MHz master clock */
  42         MC_TCK_D5 = 0x8B, /* Enable /5 div, backward compat to FT2232D */
  43         MC_EN_3PH_CLK = 0x8C, /* Enable 3 phase clk, DDR I2C */
  44         MC_DIS_3PH_CLK = 0x8D, /* Disable 3 phase clk */
  45         MC_CLK_N = 0x8E, /* Clock every bit, used for JTAG */
  46         MC_CLK_N8 = 0x8F, /* Clock every byte, used for JTAG */
  47         MC_CLK_TO_H = 0x94, /* Clock until GPIOL1 goes high */
  48         MC_CLK_TO_L = 0x95, /* Clock until GPIOL1 goes low */
  49         MC_EN_ADPT_CLK = 0x96, /* Enable adaptive clocking */
  50         MC_DIS_ADPT_CLK = 0x97, /* Disable adaptive clocking */
  51         MC_CLK8_TO_H = 0x9C, /* Clock until GPIOL1 goes high, count bytes */
  52         MC_CLK8_TO_L = 0x9D, /* Clock until GPIOL1 goes low, count bytes */
  53         MC_TRI = 0x9E, /* Set IO to only drive on 0 and tristate on 1 */
  54         /* CPU mode commands */
  55         MC_CPU_RS = 0x90, /* CPUMode read short address */
  56         MC_CPU_RE = 0x91, /* CPUMode read extended address */
  57         MC_CPU_WS = 0x92, /* CPUMode write short address */
  58         MC_CPU_WE = 0x93, /* CPUMode write extended address */
  59 };
  60
  61
  62 /* Transfer Command bits */
  63
  64 /* All byte based commands consist of:
  65  * - Command byte
  66  * - Length lsb
  67  * - Length msb
  68  *
  69  * If data out is enabled the data follows after the above command bytes,
  70  * otherwise no additional data is needed.
  71  * - Data * n
  72  *
  73  * All bit based commands consist of:
  74  * - Command byte
  75  * - Length
  76  *
  77  * If data out is enabled a byte containing bitst to transfer follows.
  78  * Otherwise no additional data is needed. Only up to 8 bits can be transferred
  79  * per transaction when in bit mode.
  80  */
  81
  82 /* b 0000 0000
  83  *   |||| |||`- Data out negative enable. Update DO on negative clock edge.
  84  *   |||| ||`-- Bit count enable. When reset count represents bytes.
  85  *   |||| |`--- Data in negative enable. Latch DI on negative clock edge.
  86  *   |||| `---- LSB enable. When set clock data out LSB first.
  87  *   ||||
  88  *   |||`------ Data out enable
  89  *   ||`------- Data in enable
  90  *   |`-------- TMS mode enable
  91  *   `--------- Special command mode enable. See mpsse_cmd enum.
  92  */
  93
  94 #define MC_DATA_TMS  (0x40) /* When set use TMS mode */
  95 #define MC_DATA_IN   (0x20) /* When set read data (Data IN) */
  96 #define MC_DATA_OUT  (0x10) /* When set write data (Data OUT) */
  97 #define MC_DATA_LSB  (0x08) /* When set input/output data LSB first. */
  98 #define MC_DATA_ICN  (0x04) /* When set receive data on negative clock edge */
  99 #define MC_DATA_BITS (0x02) /* When set count bits not bytes */
 100 #define MC_DATA_OCN  (0x01) /* When set update data on negative clock edge */
 101
 102
 103 void mpsse_check_rx(void);
 104 void mpsse_error(int status);
 105 uint8_t mpsse_recv_byte(void);
 106 void mpsse_send_byte(uint8_t data);
 107 void mpsse_send_spi(uint8_t *data, int n);
 108 void mpsse_xfer_spi(uint8_t *data, int n);
 109 uint8_t mpsse_xfer_spi_bits(uint8_t data, int n);
 110 void mpsse_set_gpio(uint8_t gpio, uint8_t direction);
 111 int mpsse_readb_low(void);
 112 int mpsse_readb_high(void);
 113 void mpsse_send_dummy_bytes(uint8_t n);
 114 void mpsse_send_dummy_bit(void);
 115 void mpsse_init(int ifnum, const char *devstr, bool slow_clock);
 116 void mpsse_close(void);
 117
 118 #endif /* MPSSE_H */