multiply.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7
   8 entity multiply is
   9     generic (
  10         PIPELINE_DEPTH : natural := 3
  11         );
  12     port (
  13         clk   : in std_logic;
  14
  15         m_in  : in MultiplyInputType;
  16         m_out : out MultiplyOutputType
  17         );
  18 end entity multiply;
  19
  20 architecture behaviour of multiply is
  21     signal m: MultiplyInputType := MultiplyInputInit;
  22
  23     type multiply_pipeline_stage is record
  24         valid     : std_ulogic;
  25         data      : unsigned(127 downto 0);
  26     end record;
  27     constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
  28                                                                      data => (others => '0'));
  29
  30     type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
  31     constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
  32
  33     type reg_type is record
  34         multiply_pipeline : multiply_pipeline_type;
  35     end record;
  36
  37     signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
  38     signal overflow : std_ulogic;
  39     signal ovf_in   : std_ulogic;
  40 begin
  41     multiply_0: process(clk)
  42     begin
  43         if rising_edge(clk) then
  44             m <= m_in;
  45             r <= rin;
  46             overflow <= ovf_in;
  47         end if;
  48     end process;
  49
  50     multiply_1: process(all)
  51         variable v : reg_type;
  52         variable a, b : std_ulogic_vector(64 downto 0);
  53         variable prod : std_ulogic_vector(129 downto 0);
  54         variable d : std_ulogic_vector(127 downto 0);
  55         variable d2 : std_ulogic_vector(63 downto 0);
  56         variable ov : std_ulogic;
  57     begin
  58         v := r;
  59         a := (m.is_signed and m.data1(63)) & m.data1;
  60         b := (m.is_signed and m.data2(63)) & m.data2;
  61         prod := std_ulogic_vector(signed(a) * signed(b));
  62         v.multiply_pipeline(0).valid := m.valid;
  63         if m.subtract = '1' then
  64             v.multiply_pipeline(0).data := unsigned(m.addend) - unsigned(prod(127 downto 0));
  65         else
  66             v.multiply_pipeline(0).data := unsigned(m.addend) + unsigned(prod(127 downto 0));
  67         end if;
  68
  69         loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
  70             v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
  71         end loop;
  72
  73         d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
  74         ov := (or d(127 downto 63)) and not (and d(127 downto 63));
  75         ovf_in <= ov;
  76
  77         m_out.result <= d;
  78         m_out.overflow <= overflow;
  79         m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
  80
  81         rin <= v;
  82     end process;
  83 end architecture behaviour;
  84
  85 library ieee;
  86 use ieee.std_logic_1164.all;
  87 use ieee.numeric_std.all;
  88
  89 entity short_multiply is
  90     port (
  91         clk   : in std_ulogic;
  92
  93         a_in  : in std_ulogic_vector(15 downto 0);
  94         b_in  : in std_ulogic_vector(15 downto 0);
  95         m_out : out std_ulogic_vector(31 downto 0)
  96         );
  97 end entity short_multiply;
  98
  99 architecture behaviour of short_multiply is
 100 begin
 101     m_out <= std_ulogic_vector(signed(a_in) * signed(b_in));
 102 end architecture behaviour;