nix/verilog.nix

   1 { version }:
   2
   3 { stdenv, python3Packages }:
   4
   5 stdenv.mkDerivation {
   6   pname = "libresoc.v";
   7   inherit version;
   8
   9   src = ../.;
  10
  11   strictDeps = true;
  12
  13   nativeBuildInputs = with python3Packages; [ nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa ];
  14
  15   configurePhase = "true";
  16
  17   buildPhase = ''
  18     runHook preBuild
  19     cd src
  20     export PYTHONPATH="$PWD:$PYTHONPATH"
  21     python3 soc/simple/issuer_verilog.py \
  22       --debug=jtag --enable-core --enable-pll \
  23       --enable-xics --enable-sram4x4kblock --disable-svp64 \
  24       libresoc.v
  25     runHook postBuild
  26   '';
  27
  28   installPhase = ''
  29     runHook preInstall
  30     mv libresoc.v $out
  31     runHook postInstall
  32   '';
  33
  34   fixupPhase = "true";
  35 }