nix/verilog.nix

   1 { version }:
   2
   3 { stdenv, python3Packages }:
   4
   5 stdenv.mkDerivation {
   6   pname = "libresoc.v";
   7   inherit version;
   8
   9   src = ../.;
  10
  11   strictDeps = true;
  12
  13   nativeBuildInputs = with python3Packages; [
  14     c4m-jtag nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa
  15   ];
  16
  17   configurePhase = "true";
  18
  19   buildPhase = ''
  20     runHook preBuild
  21     cd src
  22     export PYTHONPATH="$PWD:$PYTHONPATH"
  23     python3 soc/simple/issuer_verilog.py \
  24       --debug=jtag --enable-core --enable-pll \
  25       --enable-xics --enable-sram4x4kblock --disable-svp64 \
  26       libresoc.v
  27     runHook postBuild
  28   '';
  29
  30   installPhase = ''
  31     runHook preInstall
  32     mv libresoc.v $out
  33     runHook postInstall
  34   '';
  35
  36   fixupPhase = "true";
  37 }