nlnet_2021_lip6_vlsi.mdwn

   1 ## Project name
   2
   3 LIP6 VLSI Tools
   4
   5 ## Website / wiki
   6
   7 <https://libre-soc.org/nlnet_2021_lip6_vlsi>
   8
   9 Please be short and to the point in your answers; focus primarily on
  10 the what and how, not so much on the why. Add longer descriptions as
  11 attachments (see below). If English isn't your first language, don't
  12 worry - our reviewers don't care about spelling errors, only about
  13 great ideas. We apologise for the inconvenience of having to submit in
  14 English. On the up side, you can be as technical as you need to be (but
  15 you don't have to). Do stay concrete. Use plain text in your reply only,
  16 if you need any HTML to make your point please include this as attachment.
  17
  18 ## Abstract: Can you explain the whole project and its expected outcome(s).
  19
  20 LIP6's VLSI tools are one of the few user-operated toolchains for creating
  21 ASIC layouts where the full source code is available for inspection.
  22 This means that there is no opportunity for insertion of rogue hardware
  23 into an ASIC made by LIP6 tools which could compromise user trust, either locally or for
  24 internet use. Further: academic, public and free discussion are all
  25 engendered and fostered where at present NDAs rife through the VLSI
  26 Industry prevent and prohibit discussion and general improvements beneficial
  27 to users.
  28
  29 The expected outcome is to improve Coriolis2, HITAS/TAGLE and extend the
  30 whole toolchain so that it is faster, able to handle larger ASIC designs,
  31 and can perform Logical Validation. Also to be improved and tested is
  32 support for lower geometries (starting with 130nm)
  33
  34 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  35
  36 LIP6 has created the ASIC Layout for the Libre-SOC 180nm ASIC that went to
  37 IMEC TSMC MPW in June 2021.  It was developed entirely with Libre source code
  38 from HDL to GDS-II, the only NDA being the TSMC PDK.
  39
  40
  41 # Requested Amount
  42
  43 EUR $50,000.
  44
  45 # Explain what the requested budget will be used for?
  46
  47
  48 # Does the project have other funding sources, both past and present?
  49
  50 LIP6 is part of Sorbonne University.  The developers and maintainers
  51 of Coriolis2, HITAS/TAGLE, and Alliance, are all employed by Sorbonne
  52 University.
  53
  54 # Compare your own project with existing or historical efforts.
  55
  56 The only other major proven VLSI Toolchain that is Libre Licensed and
  57 has created successful ASICs is Magic, selected as part of the OpenROAD
  58 toolchain.  The entire OpenROAD toolchain is based on tcl/tk, a late 1980s
  59 scripting language technology.  LIP6 VLSI tools are written in c++ and python,
  60 which are modern much better well-known programming languages. With python
  61 being so well-known and prevalent it is much easier to operate and
  62 coriolis2
  63 for the development of complex reproducible ASIC layouts.
  64
  65 ## What are significant technical challenges you expect to solve during the project, if any?
  66
  67
  68 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
  69
  70
  71
  72 # Extra info to be submitted