nlnet_2022_ongoing.mdwn

   1 # NL.net proposal
   2
   3 2022-08-
   4
   5 ## Project name
   6
   7 Libre-SOC Ongoing 2022/3
   8
   9 ## Website / wiki
  10
  11 <https://libre-soc.org/nlnet_2022_ongoing>
  12
  13 Please be short and to the point in your answers; focus primarily on
  14 the what and how, not so much on the why. Add longer descriptions as
  15 attachments (see below). If English isn't your first language, don't
  16 worry - our reviewers don't care about spelling errors, only about
  17 great ideas. We apologise for the inconvenience of having to submit in
  18 English. On the up side, you can be as technical as you need to be (but
  19 you don't have to). Do stay concrete. Use plain text in your reply only,
  20 if you need any HTML to make your point please include this as attachment.
  21
  22 ## Abstract: Can you explain the whole project and its expected outcome(s).
  23
  24 Libre-SOC aims to create a Supercomputing-class entirely Libre Hybrid
  25 CPU-VPU-GPU. In proposal 2022-08-51 we aim to begin the long process
  26 of submitting the required Scalable Vector Extension to the OpenPOWER
  27 Foundation: this Grant Request focusses more on continuing to
  28 *implement* that Scalable Vector Extension.
  29
  30 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
  31
  32 As mentioned in 2022-08-51,
  33 a lot! a full list is maintained here <https://libre-soc.org/nlnet_proposals/>
  34 and includes
  35
  36 * the world's first FOSSHW IEEE754 Formal Correctness Proofs for fadd, fsub, and fma, with support for FP Formal Proofs added to symbiyosis;
  37 * the world's first in-place Discrete Cosine Transform algorithm;
  38 * Significant improvements to Europe's only silicon-proven FOSSHW VLSI toolchain (coriolis2, by LIP6 Labs of Sorbonne University)
  39  to do an 800,000 transistor fully automated RTL2GDSII
  40 tape-out;
  41 * development of a 180nm Power ISA 3.0 "Test ASIC", the largest fully FOSSHW
  42   ASIC ever taped-out in Europe (and funded by Horizon 2020)
  43 * development of an Interoperability "Test API" for Power ISA systems,
  44   with thousands of unit tests.
  45
  46 and much more. The side-benefits alone for EU citizens are enormous.
  47
  48 # Requested Amount
  49
  50 EUR 100,000.
  51
  52 # Explain what the requested budget will be used for?
  53
  54 Whilst 2022-08-51 focusses on submitting SVP64 to the OpenPOWER ISA WG,
  55 and satisfying Voting Members of its suitability, we need to proceed
  56 with implementing SVP64 and underlying infrastructure:
  57
  58 * Dynamic Partitioned SIMD for nmigen
  59 * Completion of IEEE754 FP Formal Correctness Proofs
  60 * Completion of an In-Order Single-Issue core implementing SVP64
  61 * Addition of the IEEE754 FPU to the Core
  62 * Addition of other ALUs and pipelines (bitmanip, video)
  63   implementing new Draft instructions from 2022-08-051
  64 * Addition of SMP (multi-core) support
  65 * Running under Verilator and on FPGAs (big ones) which will
  66   need to be investigated, bought, and the Libre-Licensed tools support
  67   potentially added or improved
  68 * Continued documentation, attendance of Conferences online
  69 * Begin investigating Multi-Issue Out-of-Order, continuing
  70   the 6600 Scoreboard research from 2019-02-012
  71 * Establishment and management of Continuous Integration
  72   infrastructure and upgrading the Libre-SOC IT systems
  73   (currently a single 4GB VM)
  74 * If there is sufficient budget we would like to begin investigating
  75   OpenCAPI (we have access to two Bitmain 250 FPGAs thanks to UOregon)
  76
  77 several more practical details which help very much to ensure that the
  78 efforts to date, funded very kindly by NLnet, reach fruition as part
  79 of providing EU Citizens with a powerful Libre alternative processor
  80 option.
  81
  82 # Compare your own project with existing or historical efforts.
  83
  84 As hinted at in 2022-08-051
  85 we are basically developing a Cray-style Supercomputer, leveraging
  86 the Supercomputing-class Power ISA
  87 and extending it.  Similar historic ISAs include
  88 Cray Y/MP, ETA-10, Cyber CDC 205. More recent is the NEC SX Aurora.
  89 They are all proprietary systems: Libre-SOC's efforts are entirely
  90 FOSSHW.
  91
  92 Whilst the European Processor Initiative is focussing exclusively
  93 on RISC-V, due to the amount of time it takes to assess an ISA's
  94 suitability it has to be said that it is being discovered, very slowly,
  95 that RISC-V is not suited to High-Performance Supercomputing
  96 workloads. The best explanation online is here:
  97 <https://news.ycombinator.com/item?id=24459041>
  98
  99 Therefore this project is a really important alternative
 100 being based on a much more suitable High-performance
 101 base that has the backing of
 102 IBM for over 25 years, and is now an Open ISA.
 103 <https://openpowerfoundation.org/blog/final-draft-of-the-power-isa-eula-released/>
 104
 105 ## What are significant technical challenges you expect to solve during the project, if any?
 106
 107 Processor design is HARD. This is dramatically underestimated.  We are
 108 therefore taking a careful and considered incremental approach, using
 109 Software Engineering programming techniques, developing unit tests
 110 at every level and ensuring rigorous documentation and Project coordination
 111 guidelines are adhered to.
 112
 113 We also make significant use of automation,
 114 compiler technology and abstraction
 115 which would never be considered by Hardware-only VLSI Engineers.
 116 By taking a step back we simplify the approach to one that is
 117 manageable by a much smaller team.
 118
 119 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 120
 121 As in 2022-08-051
 122 we are already set to submit presentations through multiple Conferences
 123 as has been ongoing since 2019 as can be seen at <https://libre-soc.org/conferences> and will continue to submit press releases to
 124 OPF <https://openpowerfoundation.org/blog/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/>. Our entire development is public
 125 so is accessible to all.
 126
 127 # Extra info to be submitted
 128