nmigen/back/pysim.pyi

   1 from ..hdl.ast import (Signal, Statement, Delay as Delay,
   2                        Tick as Tick, Passive as Passive, Assign, Value)
   3 from typing import Any, Iterable, Generator, Union, Callable, Optional
   4
   5 __all__ = ["Simulator", "Delay", "Tick", "Passive", "DeadlineError"]
   6
   7 ProcessCommand = Union[Delay, Tick, Passive, Assign, Value]
   8 ProcessGenerator = Generator[ProcessCommand, Union[int, None], None]
   9 Process = Union[ProcessGenerator, Callable[[], ProcessGenerator]]
  10
  11
  12 class Simulator:
  13     def __init__(self,
  14                  fragment: Any,
  15                  vcd_file: Any = None,
  16                  gtkw_file: Any = None,
  17                  traces: Iterable[Signal] = ()):
  18         ...
  19
  20     def __enter__(self) -> 'Simulator':
  21         ...
  22
  23     def __exit__(self, *args: Any) -> None:
  24         ...
  25
  26     def add_process(self, process: Process) -> None:
  27         ...
  28
  29     def add_sync_process(self, process: Process) -> None:
  30         ...
  31
  32     def add_clock(self,
  33                   period: float,
  34                   phase: Optional[float] = None,
  35                   domain: Any = "sync") -> None:
  36         ...
  37
  38     def step(self, run_passive: bool = False) -> bool:
  39         ...
  40
  41     def run(self) -> None:
  42         ...
  43
  44     def run_until(self, deadline: float, run_passive: bool = False) -> bool:
  45         ...