nmigen/back/verilog.py

   1 from .._toolchain.yosys import *
   2 from . import rtlil
   3
   4
   5 __all__ = ["YosysError", "convert", "convert_fragment"]
   6
   7
   8 def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()):
   9     # this version requirement needs to be synchronized with the one in setup.py!
  10     yosys = find_yosys(lambda ver: ver >= (0, 9))
  11     yosys_version = yosys.version()
  12
  13     script = []
  14     script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))
  15
  16     if yosys_version >= (0, 9, 3468):
  17         # Yosys >=0.9+3468 (since commit 128522f1) emits the workaround for the `always @*`
  18         # initial scheduling issue on its own.
  19         script.append("delete w:$verilog_initial_trigger")
  20
  21     if yosys_version >= (0, 9, 3527):
  22         # Yosys >=0.9+3527 (since commit 656ee70f) supports the `-nomux` option for the `proc`
  23         # script pass. Because the individual `proc_*` passes are not a stable interface,
  24         # `proc -nomux` is used instead, if available.
  25         script.append("proc -nomux")
  26     else:
  27         # On earlier versions, use individual `proc_*` passes; this is a known range of Yosys
  28         # versions and we know it's compatible with what nMigen does.
  29         script.append("proc_init")
  30         script.append("proc_arst")
  31         script.append("proc_dff")
  32         script.append("proc_clean")
  33     script.append("memory_collect")
  34
  35     if strip_internal_attrs:
  36         attr_map = []
  37         attr_map.append("-remove generator")
  38         attr_map.append("-remove top")
  39         attr_map.append("-remove src")
  40         attr_map.append("-remove nmigen.hierarchy")
  41         attr_map.append("-remove nmigen.decoding")
  42         script.append("attrmap {}".format(" ".join(attr_map)))
  43         script.append("attrmap -modattr {}".format(" ".join(attr_map)))
  44
  45     script.append("write_verilog -norename {}".format(" ".join(write_verilog_opts)))
  46
  47     return yosys.run(["-q", "-"], "\n".join(script),
  48         # At the moment, Yosys always shows a warning indicating that not all processes can be
  49         # translated to Verilog. We carefully emit only the processes that *can* be translated, and
  50         # squash this warning. Once Yosys' write_verilog pass is fixed, we should remove this.
  51         ignore_warnings=True)
  52
  53
  54 def convert_fragment(*args, strip_internal_attrs=False, **kwargs):
  55     rtlil_text, name_map = rtlil.convert_fragment(*args, **kwargs)
  56     return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs), name_map
  57
  58
  59 def convert(*args, strip_internal_attrs=False, **kwargs):
  60     rtlil_text = rtlil.convert(*args, **kwargs)
  61     return _convert_rtlil_text(rtlil_text, strip_internal_attrs=strip_internal_attrs)