nmigen/cli.py

   1 import argparse
   2
   3 from .hdl.ir import Fragment
   4 from .back import rtlil, cxxrtl, verilog, pysim
   5
   6
   7 __all__ = ["main"]
   8
   9
  10 def main_parser(parser=None):
  11     if parser is None:
  12         parser = argparse.ArgumentParser()
  13
  14     p_action = parser.add_subparsers(dest="action")
  15
  16     p_generate = p_action.add_parser("generate",
  17         help="generate RTLIL, Verilog or CXXRTL from the design")
  18     p_generate.add_argument("-t", "--type", dest="generate_type",
  19         metavar="LANGUAGE", choices=["il", "cc", "v"],
  20         help="generate LANGUAGE (il for RTLIL, v for Verilog, cc for CXXRTL; default: file extension of FILE, if given)")
  21     p_generate.add_argument("generate_file",
  22         metavar="FILE", type=argparse.FileType("w"), nargs="?",
  23         help="write generated code to FILE")
  24
  25     p_simulate = p_action.add_parser(
  26         "simulate", help="simulate the design")
  27     p_simulate.add_argument("-v", "--vcd-file",
  28         metavar="VCD-FILE", type=argparse.FileType("w"),
  29         help="write execution trace to VCD-FILE")
  30     p_simulate.add_argument("-w", "--gtkw-file",
  31         metavar="GTKW-FILE", type=argparse.FileType("w"),
  32         help="write GTKWave configuration to GTKW-FILE")
  33     p_simulate.add_argument("-p", "--period", dest="sync_period",
  34         metavar="TIME", type=float, default=1e-6,
  35         help="set 'sync' clock domain period to TIME (default: %(default)s)")
  36     p_simulate.add_argument("-c", "--clocks", dest="sync_clocks",
  37         metavar="COUNT", type=int, required=True,
  38         help="simulate for COUNT 'sync' clock periods")
  39
  40     return parser
  41
  42
  43 def main_runner(parser, args, design, platform=None, name="top", ports=()):
  44     if args.action == "generate":
  45         fragment = Fragment.get(design, platform)
  46         generate_type = args.generate_type
  47         if generate_type is None and args.generate_file:
  48             if args.generate_file.name.endswith(".il"):
  49                 generate_type = "il"
  50             if args.generate_file.name.endswith(".cc"):
  51                 generate_type = "cc"
  52             if args.generate_file.name.endswith(".v"):
  53                 generate_type = "v"
  54         if generate_type is None:
  55             parser.error("Unable to auto-detect language, specify explicitly with -t/--type")
  56         if generate_type == "il":
  57             output = rtlil.convert(fragment, name=name, ports=ports)
  58         if generate_type == "cc":
  59             output = cxxrtl.convert(fragment, name=name, ports=ports)
  60         if generate_type == "v":
  61             output = verilog.convert(fragment, name=name, ports=ports)
  62         if args.generate_file:
  63             args.generate_file.write(output)
  64         else:
  65             print(output)
  66
  67     if args.action == "simulate":
  68         fragment = Fragment.get(design, platform)
  69         sim = pysim.Simulator(fragment)
  70         sim.add_clock(args.sync_period)
  71         with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
  72             sim.run_until(args.sync_period * args.sync_clocks, run_passive=True)
  73
  74
  75 def main(*args, **kwargs):
  76     parser = main_parser()
  77     main_runner(parser, parser.parse_args(), *args, **kwargs)