nmigen/hdl/mem.pyi

   1 from typing import Optional, Iterable, List, Union
   2 from .ast import Signal, Const
   3
   4 __all__ = ["Memory", "ReadPort", "WritePort", "DummyPort"]
   5
   6
   7 class ReadPort:
   8     memory: 'Memory'
   9     domain: str
  10     synchronous: bool
  11     transparent: bool
  12     addr: Signal
  13     data: Signal
  14     en: Union[Signal, Const]
  15
  16
  17 class WritePort:
  18     memory: 'Memory'
  19     domain: str
  20     priority: int
  21     granularity: int
  22     addr: Signal
  23     data: Signal
  24     en: Signal
  25
  26
  27 class Memory:
  28     width: int
  29     depth: int
  30     name: str
  31
  32     def __init__(self,
  33                  width: int,
  34                  depth: int,
  35                  init: Optional[Iterable[int]] = None,
  36                  name: Optional[str] = None,
  37                  simulate: bool = True):
  38         ...
  39
  40     @property
  41     def init(self) -> List[int]:
  42         ...
  43
  44     @init.setter
  45     def init(self, new_init: Optional[Iterable[int]]) -> None:
  46         ...
  47
  48     def read_port(self,
  49                   domain: str = "sync",
  50                   synchronous: bool = True,
  51                   transparent: bool = True) -> ReadPort:
  52         ...
  53
  54     def write_port(self,
  55                    domain: str = "sync",
  56                    priority: int = 0,
  57                    granularity: Optional[int] = None) -> WritePort:
  58         ...