sim: split into base, core, and engines.
[nmigen.git] / nmigen / sim / _pyclock.py
1 import inspect
2
3 from ._base import BaseProcess
4
5
6 __all__ = ["PyClockProcess"]
7
8
9 class PyClockProcess(BaseProcess):
10 def __init__(self, state, signal, *, phase, period):
11 assert len(signal) == 1
12
13 self.state = state
14 self.slot = self.state.get_signal(signal)
15 self.phase = phase
16 self.period = period
17
18 self.reset()
19
20 def reset(self):
21 self.runnable = True
22 self.passive = True
23
24 self.initial = True
25
26 def run(self):
27 self.runnable = False
28
29 if self.initial:
30 self.initial = False
31 self.state.wait_interval(self, self.phase)
32
33 else:
34 clk_state = self.state.slots[self.slot]
35 clk_state.set(not clk_state.curr)
36 self.state.wait_interval(self, self.period / 2)