nmigen/test/test_hdl_cd.py

   1 from ..hdl.cd import *
   2 from .utils import *
   3
   4
   5 class ClockDomainTestCase(FHDLTestCase):
   6     def test_name(self):
   7         sync = ClockDomain()
   8         self.assertEqual(sync.name, "sync")
   9         self.assertEqual(sync.clk.name, "clk")
  10         self.assertEqual(sync.rst.name, "rst")
  11         self.assertEqual(sync.local, False)
  12         pix = ClockDomain()
  13         self.assertEqual(pix.name, "pix")
  14         self.assertEqual(pix.clk.name, "pix_clk")
  15         self.assertEqual(pix.rst.name, "pix_rst")
  16         cd_pix = ClockDomain()
  17         self.assertEqual(pix.name, "pix")
  18         dom = [ClockDomain("foo")][0]
  19         self.assertEqual(dom.name, "foo")
  20         with self.assertRaises(ValueError,
  21                 msg="Clock domain name must be specified explicitly"):
  22             ClockDomain()
  23         cd_reset = ClockDomain(local=True)
  24         self.assertEqual(cd_reset.local, True)
  25
  26     def test_edge(self):
  27         sync = ClockDomain()
  28         self.assertEqual(sync.clk_edge, "pos")
  29         sync = ClockDomain(clk_edge="pos")
  30         self.assertEqual(sync.clk_edge, "pos")
  31         sync = ClockDomain(clk_edge="neg")
  32         self.assertEqual(sync.clk_edge, "neg")
  33
  34     def test_edge_wrong(self):
  35         with self.assertRaises(ValueError,
  36                 msg="Domain clock edge must be one of 'pos' or 'neg', not 'xxx'"):
  37             ClockDomain("sync", clk_edge="xxx")
  38
  39     def test_with_reset(self):
  40         pix = ClockDomain()
  41         self.assertIsNotNone(pix.clk)
  42         self.assertIsNotNone(pix.rst)
  43         self.assertFalse(pix.async_reset)
  44
  45     def test_without_reset(self):
  46         pix = ClockDomain(reset_less=True)
  47         self.assertIsNotNone(pix.clk)
  48         self.assertIsNone(pix.rst)
  49         self.assertFalse(pix.async_reset)
  50
  51     def test_async_reset(self):
  52         pix = ClockDomain(async_reset=True)
  53         self.assertIsNotNone(pix.clk)
  54         self.assertIsNotNone(pix.rst)
  55         self.assertTrue(pix.async_reset)
  56
  57     def test_rename(self):
  58         sync = ClockDomain()
  59         self.assertEqual(sync.name, "sync")
  60         self.assertEqual(sync.clk.name, "clk")
  61         self.assertEqual(sync.rst.name, "rst")
  62         sync.rename("pix")
  63         self.assertEqual(sync.name, "pix")
  64         self.assertEqual(sync.clk.name, "pix_clk")
  65         self.assertEqual(sync.rst.name, "pix_rst")
  66
  67     def test_rename_reset_less(self):
  68         sync = ClockDomain(reset_less=True)
  69         self.assertEqual(sync.name, "sync")
  70         self.assertEqual(sync.clk.name, "clk")
  71         sync.rename("pix")
  72         self.assertEqual(sync.name, "pix")
  73         self.assertEqual(sync.clk.name, "pix_clk")
  74
  75     def test_wrong_name_comb(self):
  76         with self.assertRaises(ValueError,
  77                 msg="Domain 'comb' may not be clocked"):
  78             comb = ClockDomain()