nmigen/test/test_lib_scheduler.py

   1 # nmigen: UnusedElaboratable=no
   2 import unittest
   3 from .utils import *
   4 from ..hdl import *
   5 from ..asserts import *
   6 from ..sim.pysim import *
   7 from ..lib.scheduler import *
   8
   9
  10 class RoundRobinTestCase(unittest.TestCase):
  11     def test_count(self):
  12         dut = RoundRobin(count=32)
  13         self.assertEqual(dut.count, 32)
  14         self.assertEqual(len(dut.requests), 32)
  15         self.assertEqual(len(dut.grant), 5)
  16
  17     def test_wrong_count(self):
  18         with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not 'foo'"):
  19             dut = RoundRobin(count="foo")
  20         with self.assertRaisesRegex(ValueError, r"Count must be a non-negative integer, not -1"):
  21             dut = RoundRobin(count=-1)
  22
  23
  24 class RoundRobinSimulationTestCase(unittest.TestCase):
  25     def test_count_one(self):
  26         dut = RoundRobin(count=1)
  27         sim = Simulator(dut)
  28         def process():
  29             yield dut.requests.eq(0)
  30             yield; yield Delay(1e-8)
  31             self.assertEqual((yield dut.grant), 0)
  32             self.assertFalse((yield dut.valid))
  33
  34             yield dut.requests.eq(1)
  35             yield; yield Delay(1e-8)
  36             self.assertEqual((yield dut.grant), 0)
  37             self.assertTrue((yield dut.valid))
  38         sim.add_sync_process(process)
  39         sim.add_clock(1e-6)
  40         with sim.write_vcd("test.vcd"):
  41             sim.run()
  42
  43     def test_transitions(self):
  44         dut = RoundRobin(count=3)
  45         sim = Simulator(dut)
  46         def process():
  47             yield dut.requests.eq(0b111)
  48             yield; yield Delay(1e-8)
  49             self.assertEqual((yield dut.grant), 1)
  50             self.assertTrue((yield dut.valid))
  51
  52             yield dut.requests.eq(0b110)
  53             yield; yield Delay(1e-8)
  54             self.assertEqual((yield dut.grant), 2)
  55             self.assertTrue((yield dut.valid))
  56
  57             yield dut.requests.eq(0b010)
  58             yield; yield Delay(1e-8)
  59             self.assertEqual((yield dut.grant), 1)
  60             self.assertTrue((yield dut.valid))
  61
  62             yield dut.requests.eq(0b011)
  63             yield; yield Delay(1e-8)
  64             self.assertEqual((yield dut.grant), 0)
  65             self.assertTrue((yield dut.valid))
  66
  67             yield dut.requests.eq(0b001)
  68             yield; yield Delay(1e-8)
  69             self.assertEqual((yield dut.grant), 0)
  70             self.assertTrue((yield dut.valid))
  71
  72             yield dut.requests.eq(0b101)
  73             yield; yield Delay(1e-8)
  74             self.assertEqual((yield dut.grant), 2)
  75             self.assertTrue((yield dut.valid))
  76
  77             yield dut.requests.eq(0b100)
  78             yield; yield Delay(1e-8)
  79             self.assertEqual((yield dut.grant), 2)
  80             self.assertTrue((yield dut.valid))
  81
  82             yield dut.requests.eq(0b000)
  83             yield; yield Delay(1e-8)
  84             self.assertFalse((yield dut.valid))
  85
  86             yield dut.requests.eq(0b001)
  87             yield; yield Delay(1e-8)
  88             self.assertEqual((yield dut.grant), 0)
  89             self.assertTrue((yield dut.valid))
  90         sim.add_sync_process(process)
  91         sim.add_clock(1e-6)
  92         with sim.write_vcd("test.vcd"):
  93             sim.run()