nmigen/vendor/lattice_ecp5.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeECP5Platform"]
   8
   9
  10 class LatticeECP5Platform(TemplatedPlatform):
  11     """
  12     Trellis toolchain
  13     -----------------
  14
  15     Required tools:
  16         * ``yosys``
  17         * ``nextpnr-ecp5``
  18         * ``ecppack``
  19
  20     The environment is populated by running the script specified in the environment variable
  21     ``NMIGEN_ENV_Trellis``, if present.
  22
  23     Available overrides:
  24         * ``verbose``: enables logging of informational messages to standard error.
  25         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  26         * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
  27         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  28         * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
  29         * ``yosys_opts``: adds extra options for ``yosys``.
  30         * ``nextpnr_opts``: adds extra options for ``nextpnr-ecp5``.
  31         * ``ecppack_opts``: adds extra options for ``ecppack``.
  32         * ``add_preferences``: inserts commands at the end of the LPF file.
  33
  34     Build products:
  35         * ``{{name}}.rpt``: Yosys log.
  36         * ``{{name}}.json``: synthesized RTL.
  37         * ``{{name}}.tim``: nextpnr log.
  38         * ``{{name}}.config``: ASCII bitstream.
  39         * ``{{name}}.bit``: binary bitstream.
  40         * ``{{name}}.svf``: JTAG programming vector.
  41
  42     Diamond toolchain
  43     -----------------
  44
  45     Required tools:
  46         * ``pnmainc``
  47         * ``ddtcmd``
  48
  49     The environment is populated by running the script specified in the environment variable
  50     ``NMIGEN_ENV_Diamond``, if present. On Linux, diamond_env as provided by Diamond
  51     itself is a good candidate. On Windows, the following script (named ``diamond_env.bat``,
  52     for instance) is known to work::
  53
  54         @echo off
  55         set PATH=C:\\lscc\\diamond\\%DIAMOND_VERSION%\\bin\\nt64;%PATH%
  56
  57     Available overrides:
  58         * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
  59         * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
  60         * ``add_preferences``: inserts commands at the end of the LPF file.
  61         * ``add_constraints``: inserts commands at the end of the XDC file.
  62
  63     Build products:
  64         * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
  65         * ``{{name}}.bit``: binary bitstream.
  66         * ``{{name}}.svf``: JTAG programming vector.
  67     """
  68
  69     toolchain = None # selected when creating platform
  70
  71     device  = abstractproperty()
  72     package = abstractproperty()
  73     speed   = abstractproperty()
  74     grade   = "C" # [C]ommercial, [I]ndustrial
  75
  76     # Trellis templates
  77
  78     _nextpnr_device_options = {
  79         "LFE5U-12F":    "--12k",
  80         "LFE5U-25F":    "--25k",
  81         "LFE5U-45F":    "--45k",
  82         "LFE5U-85F":    "--85k",
  83         "LFE5UM-25F":   "--um-25k",
  84         "LFE5UM-45F":   "--um-45k",
  85         "LFE5UM-85F":   "--um-85k",
  86         "LFE5UM5G-25F": "--um5g-25k",
  87         "LFE5UM5G-45F": "--um5g-45k",
  88         "LFE5UM5G-85F": "--um5g-85k",
  89     }
  90     _nextpnr_package_options = {
  91         "BG256": "caBGA256",
  92         "MG285": "csfBGA285",
  93         "BG381": "caBGA381",
  94         "BG554": "caBGA554",
  95         "BG756": "caBGA756",
  96     }
  97
  98     _trellis_required_tools = [
  99         "yosys",
 100         "nextpnr-ecp5",
 101         "ecppack"
 102     ]
 103     _trellis_file_templates = {
 104         **TemplatedPlatform.build_script_templates,
 105         "{{name}}.il": r"""
 106             # {{autogenerated}}
 107             {{emit_rtlil()}}
 108         """,
 109         "{{name}}.debug.v": r"""
 110             /* {{autogenerated}} */
 111             {{emit_debug_verilog()}}
 112         """,
 113         "{{name}}.ys": r"""
 114             # {{autogenerated}}
 115             {% for file in platform.iter_extra_files(".v") -%}
 116                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
 117             {% endfor %}
 118             {% for file in platform.iter_extra_files(".sv") -%}
 119                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
 120             {% endfor %}
 121             {% for file in platform.iter_extra_files(".il") -%}
 122                 read_ilang {{file}}
 123             {% endfor %}
 124             read_ilang {{name}}.il
 125             delete w:$verilog_initial_trigger
 126             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
 127             synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
 128             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
 129             write_json {{name}}.json
 130         """,
 131         "{{name}}.lpf": r"""
 132             # {{autogenerated}}
 133             BLOCK ASYNCPATHS;
 134             BLOCK RESETPATHS;
 135             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 136                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 137                 {% if attrs -%}
 138                 IOBUF PORT "{{port_name}}"
 139                     {%- for key, value in attrs.items() %} {{key}}={{value}}{% endfor %};
 140                 {% endif %}
 141             {% endfor %}
 142             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 143                 {% if port_signal is not none -%}
 144                     FREQUENCY PORT "{{port_signal.name}}" {{frequency}} HZ;
 145                 {% else -%}
 146                     FREQUENCY NET "{{net_signal|hierarchy(".")}}" {{frequency}} HZ;
 147                 {% endif %}
 148             {% endfor %}
 149             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 150         """
 151     }
 152     _trellis_command_templates = [
 153         r"""
 154         {{invoke_tool("yosys")}}
 155             {{quiet("-q")}}
 156             {{get_override("yosys_opts")|options}}
 157             -l {{name}}.rpt
 158             {{name}}.ys
 159         """,
 160         r"""
 161         {{invoke_tool("nextpnr-ecp5")}}
 162             {{quiet("--quiet")}}
 163             {{get_override("nextpnr_opts")|options}}
 164             --log {{name}}.tim
 165             {{platform._nextpnr_device_options[platform.device]}}
 166             --package {{platform._nextpnr_package_options[platform.package]|upper}}
 167             --speed {{platform.speed}}
 168             --json {{name}}.json
 169             --lpf {{name}}.lpf
 170             --textcfg {{name}}.config
 171         """,
 172         r"""
 173         {{invoke_tool("ecppack")}}
 174             {{verbose("--verbose")}}
 175             {{get_override("ecppack_opts")|options}}
 176             --input {{name}}.config
 177             --bit {{name}}.bit
 178             --svf {{name}}.svf
 179         """
 180     ]
 181
 182     # Diamond templates
 183
 184     _diamond_required_tools = [
 185         "pnmainc",
 186         "ddtcmd"
 187     ]
 188     _diamond_file_templates = {
 189         **TemplatedPlatform.build_script_templates,
 190         "build_{{name}}.sh": r"""
 191             # {{autogenerated}}
 192             set -e{{verbose("x")}}
 193             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
 194             if [ -n "${{platform._toolchain_env_var}}" ]; then
 195                 bindir=$(dirname "${{platform._toolchain_env_var}}")
 196                 . "${{platform._toolchain_env_var}}"
 197             fi
 198             {{emit_commands("sh")}}
 199         """,
 200         "{{name}}.v": r"""
 201             /* {{autogenerated}} */
 202             {{emit_verilog()}}
 203         """,
 204         "{{name}}.debug.v": r"""
 205             /* {{autogenerated}} */
 206             {{emit_debug_verilog()}}
 207         """,
 208         "{{name}}.tcl": r"""
 209             prj_project new -name {{name}} -impl impl -impl_dir {{name}}_impl \
 210                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
 211                 -lpf {{name}}.lpf \
 212                 -synthesis synplify
 213             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
 214                 prj_src add {{file|tcl_escape}}
 215             {% endfor %}
 216             prj_src add {{name}}.v
 217             prj_impl option top {{name}}
 218             prj_src add {{name}}.sdc
 219             {{get_override("script_project")|default("# (script_project placeholder)")}}
 220             prj_project save
 221             prj_run Synthesis -impl impl -forceAll
 222             prj_run Translate -impl impl -forceAll
 223             prj_run Map -impl impl -forceAll
 224             prj_run PAR -impl impl -forceAll
 225             prj_run Export -impl impl -forceAll -task Bitgen
 226             {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
 227         """,
 228         "{{name}}.lpf": r"""
 229             # {{autogenerated}}
 230             BLOCK ASYNCPATHS;
 231             BLOCK RESETPATHS;
 232             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
 233                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 234                 IOBUF PORT "{{port_name}}"
 235                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
 236             {% endfor %}
 237             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 238         """,
 239         "{{name}}.sdc": r"""
 240             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 241                 {% if port_signal is not none -%}
 242                     create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 243                 {% else -%}
 244                     create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 245                 {% endif %}
 246             {% endfor %}
 247             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 248         """,
 249     }
 250     _diamond_command_templates = [
 251         # These don't have any usable command-line option overrides.
 252         r"""
 253         {{invoke_tool("pnmainc")}}
 254             {{name}}.tcl
 255         """,
 256         r"""
 257         {{invoke_tool("ddtcmd")}}
 258             -oft -bit
 259             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
 260         """,
 261         r"""
 262         {{invoke_tool("ddtcmd")}}
 263             -oft -svfsingle -revd -op "Fast Program"
 264             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.svf
 265         """,
 266     ]
 267
 268     # Common logic
 269
 270     def __init__(self, *, toolchain="Trellis"):
 271         super().__init__()
 272
 273         assert toolchain in ("Trellis", "Diamond")
 274         self.toolchain = toolchain
 275
 276     @property
 277     def required_tools(self):
 278         if self.toolchain == "Trellis":
 279             return self._trellis_required_tools
 280         if self.toolchain == "Diamond":
 281             return self._diamond_required_tools
 282         assert False
 283
 284     @property
 285     def file_templates(self):
 286         if self.toolchain == "Trellis":
 287             return self._trellis_file_templates
 288         if self.toolchain == "Diamond":
 289             return self._diamond_file_templates
 290         assert False
 291
 292     @property
 293     def command_templates(self):
 294         if self.toolchain == "Trellis":
 295             return self._trellis_command_templates
 296         if self.toolchain == "Diamond":
 297             return self._diamond_command_templates
 298         assert False
 299
 300     @property
 301     def default_clk_constraint(self):
 302         if self.default_clk == "OSCG":
 303             return Clock(310e6 / self.oscg_div)
 304         return super().default_clk_constraint
 305
 306     def create_missing_domain(self, name):
 307         # Lattice ECP5 devices have two global set/reset signals: PUR, which is driven at startup
 308         # by the configuration logic and unconditionally resets every storage element, and GSR,
 309         # which is driven by user logic and each storage element may be configured as affected or
 310         # unaffected by GSR. PUR is purely asynchronous, so even though it is a low-skew global
 311         # network, its deassertion may violate a setup/hold constraint with relation to a user
 312         # clock. To avoid this, a GSR/SGSR instance should be driven synchronized to user clock.
 313         if name == "sync" and self.default_clk is not None:
 314             m = Module()
 315             if self.default_clk == "OSCG":
 316                 if not hasattr(self, "oscg_div"):
 317                     raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
 318                                      "and 128")
 319                 if not isinstance(self.oscg_div, int) or self.oscg_div < 2 or self.oscg_div > 128:
 320                     raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
 321                                      "and 128, not {!r}"
 322                                      .format(self.oscg_div))
 323                 clk_i = Signal()
 324                 m.submodules += Instance("OSCG", p_DIV=self.oscg_div, o_OSC=clk_i)
 325             else:
 326                 clk_i = self.request(self.default_clk).i
 327             if self.default_rst is not None:
 328                 rst_i = self.request(self.default_rst).i
 329             else:
 330                 rst_i = Const(0)
 331
 332             gsr0 = Signal()
 333             gsr1 = Signal()
 334             # There is no end-of-startup signal on ECP5, but PUR is released after IOB enable, so
 335             # a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
 336             m.submodules += [
 337                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
 338                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
 339                 # Although we already synchronize the reset input to user clock, SGSR has dedicated
 340                 # clock routing to the center of the FPGA; use that just in case it turns out to be
 341                 # more reliable. (None of this is documented.)
 342                 Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
 343             ]
 344             # GSR implicitly connects to every appropriate storage element. As such, the sync
 345             # domain is reset-less; domains driven by other clocks would need to have dedicated
 346             # reset circuitry or otherwise meet setup/hold constraints on their own.
 347             m.domains += ClockDomain("sync", reset_less=True)
 348             m.d.comb += ClockSignal("sync").eq(clk_i)
 349             return m
 350
 351     _single_ended_io_types = [
 352         "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
 353         "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
 354     ]
 355     _differential_io_types = [
 356         "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
 357         "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
 358         "SLVS", "SSTL135D_I", "SSTL135D_II", "SSTL15D_I", "SSTL15D_II", "SSTL18D_I",
 359         "SSTL18D_II", "SUBLVDS",
 360     ]
 361
 362     def should_skip_port_component(self, port, attrs, component):
 363         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 364         # the PIOA or PIOC location, which is always the non-inverting pin.
 365         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 366             return True
 367         return False
 368
 369     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 370         def get_ireg(clk, d, q):
 371             for bit in range(len(q)):
 372                 m.submodules += Instance("IFS1P3DX",
 373                     i_SCLK=clk,
 374                     i_SP=Const(1),
 375                     i_CD=Const(0),
 376                     i_D=d[bit],
 377                     o_Q=q[bit]
 378                 )
 379
 380         def get_oreg(clk, d, q):
 381             for bit in range(len(q)):
 382                 m.submodules += Instance("OFS1P3DX",
 383                     i_SCLK=clk,
 384                     i_SP=Const(1),
 385                     i_CD=Const(0),
 386                     i_D=d[bit],
 387                     o_Q=q[bit]
 388                 )
 389
 390         def get_iddr(sclk, d, q0, q1):
 391             for bit in range(len(d)):
 392                 m.submodules += Instance("IDDRX1F",
 393                     i_SCLK=sclk,
 394                     i_RST=Const(0),
 395                     i_D=d[bit],
 396                     o_Q0=q0[bit], o_Q1=q1[bit]
 397                 )
 398
 399         def get_iddrx2(sclk, eclk, d, q0, q1, q2, q3):
 400             for bit in range(len(d)):
 401                 m.submodules += Instance("IDDRX2F",
 402                     i_SCLK=sclk,
 403                     i_ECLK=eclk,
 404                     i_RST=Const(0),
 405                     i_D=d[bit],
 406                     o_Q0=q0[bit], o_Q1=q1[bit], o_Q2=q2[bit], o_Q3=q3[bit]
 407                 )
 408
 409         def get_iddr71b(sclk, eclk, d, q0, q1, q2, q3, q4, q5, q6):
 410             for bit in range(len(d)):
 411                 m.submodules += Instance("IDDR71B",
 412                     i_SCLK=sclk,
 413                     i_ECLK=eclk,
 414                     i_RST=Const(0),
 415                     i_D=d[bit],
 416                     o_Q0=q0[bit], o_Q1=q1[bit], o_Q2=q2[bit], o_Q3=q3[bit],
 417                     o_Q4=q4[bit], o_Q5=q5[bit], o_Q6=q6[bit],
 418                 )
 419
 420         def get_oddr(sclk, d0, d1, q):
 421             for bit in range(len(q)):
 422                 m.submodules += Instance("ODDRX1F",
 423                     i_SCLK=sclk,
 424                     i_RST=Const(0),
 425                     i_D0=d0[bit], i_D1=d1[bit],
 426                     o_Q=q[bit]
 427                 )
 428
 429         def get_oddrx2(sclk, eclk, d0, d1, d2, d3, q):
 430             for bit in range(len(q)):
 431                 m.submodules += Instance("ODDRX2F",
 432                     i_SCLK=sclk,
 433                     i_ECLK=eclk,
 434                     i_RST=Const(0),
 435                     i_D0=d0[bit], i_D1=d1[bit], i_D2=d2[bit], i_D3=d3[bit],
 436                     o_Q=q[bit]
 437                 )
 438
 439         def get_oddr71b(sclk, eclk, d0, d1, d2, d3, d4, d5, d6, q):
 440             for bit in range(len(q)):
 441                 m.submodules += Instance("ODDR71B",
 442                     i_SCLK=sclk,
 443                     i_ECLK=eclk,
 444                     i_RST=Const(0),
 445                     i_D0=d0[bit], i_D1=d1[bit], i_D2=d2[bit], i_D3=d3[bit],
 446                     i_D4=d4[bit], i_D5=d5[bit], i_D6=d6[bit],
 447                     o_Q=q[bit]
 448                 )
 449
 450         def get_ineg(z, invert):
 451             if invert:
 452                 a = Signal.like(z, name_suffix="_n")
 453                 m.d.comb += z.eq(~a)
 454                 return a
 455             else:
 456                 return z
 457
 458         def get_oneg(a, invert):
 459             if invert:
 460                 z = Signal.like(a, name_suffix="_n")
 461                 m.d.comb += z.eq(~a)
 462                 return z
 463             else:
 464                 return a
 465
 466         if "i" in pin.dir:
 467             if pin.xdr < 2:
 468                 pin_i  = get_ineg(pin.i,  i_invert)
 469             elif pin.xdr == 2:
 470                 pin_i0 = get_ineg(pin.i0, i_invert)
 471                 pin_i1 = get_ineg(pin.i1, i_invert)
 472             elif pin.xdr == 4:
 473                 pin_i0 = get_ineg(pin.i0, i_invert)
 474                 pin_i1 = get_ineg(pin.i1, i_invert)
 475                 pin_i2 = get_ineg(pin.i2, i_invert)
 476                 pin_i3 = get_ineg(pin.i3, i_invert)
 477             elif pin.xdr == 7:
 478                 pin_i0 = get_ineg(pin.i0, i_invert)
 479                 pin_i1 = get_ineg(pin.i1, i_invert)
 480                 pin_i2 = get_ineg(pin.i2, i_invert)
 481                 pin_i3 = get_ineg(pin.i3, i_invert)
 482                 pin_i4 = get_ineg(pin.i4, i_invert)
 483                 pin_i5 = get_ineg(pin.i5, i_invert)
 484                 pin_i6 = get_ineg(pin.i6, i_invert)
 485         if "o" in pin.dir:
 486             if pin.xdr < 2:
 487                 pin_o  = get_oneg(pin.o,  o_invert)
 488             elif pin.xdr == 2:
 489                 pin_o0 = get_oneg(pin.o0, o_invert)
 490                 pin_o1 = get_oneg(pin.o1, o_invert)
 491             elif pin.xdr == 4:
 492                 pin_o0 = get_oneg(pin.o0, o_invert)
 493                 pin_o1 = get_oneg(pin.o1, o_invert)
 494                 pin_o2 = get_oneg(pin.o2, o_invert)
 495                 pin_o3 = get_oneg(pin.o3, o_invert)
 496             elif pin.xdr == 7:
 497                 pin_o0 = get_oneg(pin.o0, o_invert)
 498                 pin_o1 = get_oneg(pin.o1, o_invert)
 499                 pin_o2 = get_oneg(pin.o2, o_invert)
 500                 pin_o3 = get_oneg(pin.o3, o_invert)
 501                 pin_o4 = get_oneg(pin.o4, o_invert)
 502                 pin_o5 = get_oneg(pin.o5, o_invert)
 503                 pin_o6 = get_oneg(pin.o6, o_invert)
 504
 505         i = o = t = None
 506         if "i" in pin.dir:
 507             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 508         if "o" in pin.dir:
 509             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 510         if pin.dir in ("oe", "io"):
 511             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 512
 513         if pin.xdr == 0:
 514             if "i" in pin.dir:
 515                 i = pin_i
 516             if "o" in pin.dir:
 517                 o = pin_o
 518             if pin.dir in ("oe", "io"):
 519                 t = ~pin.oe
 520         elif pin.xdr == 1:
 521             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 522             if "i" in pin.dir:
 523                 get_ireg(pin.i_clk, i, pin_i)
 524             if "o" in pin.dir:
 525                 get_oreg(pin.o_clk, pin_o, o)
 526             if pin.dir in ("oe", "io"):
 527                 get_oreg(pin.o_clk, ~pin.oe, t)
 528         elif pin.xdr == 2:
 529             if "i" in pin.dir:
 530                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 531             if "o" in pin.dir:
 532                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 533             if pin.dir in ("oe", "io"):
 534                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 535                 # It is not clear what is the recommended set of primitives for this task.
 536                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 537                 get_oreg(pin.o_clk, ~pin.oe, t)
 538         elif pin.xdr == 4:
 539             if "i" in pin.dir:
 540                 get_iddrx2(pin.i_clk, pin.i_fclk, i, pin_i0, pin_i1, pin_i2, pin_i3)
 541             if "o" in pin.dir:
 542                 get_oddrx2(pin.o_clk, pin.o_fclk, pin_o0, pin_o1, pin_o2, pin_o3, o)
 543             if pin.dir in ("oe", "io"):
 544                 get_oreg(pin.o_clk, ~pin.oe, t)
 545         elif pin.xdr == 7:
 546             if "i" in pin.dir:
 547                 get_iddr71b(pin.i_clk, pin.i_fclk, i, pin_i0, pin_i1, pin_i2, pin_i3, pin_i4, pin_i5, pin_i6)
 548             if "o" in pin.dir:
 549                 get_oddr71b(pin.o_clk, pin.o_fclk, pin_o0, pin_o1, pin_o2, pin_o3, pin_o4, pin_o5, pin_o6, o)
 550             if pin.dir in ("oe", "io"):
 551                 get_oreg(pin.o_clk, ~pin.oe, t)
 552         else:
 553             assert False
 554
 555         return (i, o, t)
 556
 557     def get_input(self, pin, port, attrs, invert):
 558         self._check_feature("single-ended input", pin, attrs,
 559                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 560         m = Module()
 561         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 562         for bit in range(pin.width):
 563             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 564                 i_I=port.io[bit],
 565                 o_O=i[bit]
 566             )
 567         return m
 568
 569     def get_output(self, pin, port, attrs, invert):
 570         self._check_feature("single-ended output", pin, attrs,
 571                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 572         m = Module()
 573         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 574         for bit in range(pin.width):
 575             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 576                 i_I=o[bit],
 577                 o_O=port.io[bit]
 578             )
 579         return m
 580
 581     def get_tristate(self, pin, port, attrs, invert):
 582         self._check_feature("single-ended tristate", pin, attrs,
 583                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 584         m = Module()
 585         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 586         for bit in range(pin.width):
 587             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 588                 i_T=t,
 589                 i_I=o[bit],
 590                 o_O=port.io[bit]
 591             )
 592         return m
 593
 594     def get_input_output(self, pin, port, attrs, invert):
 595         self._check_feature("single-ended input/output", pin, attrs,
 596                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 597         m = Module()
 598         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 599         for bit in range(pin.width):
 600             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 601                 i_T=t,
 602                 i_I=o[bit],
 603                 o_O=i[bit],
 604                 io_B=port.io[bit]
 605             )
 606         return m
 607
 608     def get_diff_input(self, pin, port, attrs, invert):
 609         self._check_feature("differential input", pin, attrs,
 610                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 611         m = Module()
 612         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 613         for bit in range(pin.width):
 614             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 615                 i_I=port.p[bit],
 616                 o_O=i[bit]
 617             )
 618         return m
 619
 620     def get_diff_output(self, pin, port, attrs, invert):
 621         self._check_feature("differential output", pin, attrs,
 622                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 623         m = Module()
 624         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 625         for bit in range(pin.width):
 626             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 627                 i_I=o[bit],
 628                 o_O=port.p[bit],
 629             )
 630         return m
 631
 632     def get_diff_tristate(self, pin, port, attrs, invert):
 633         self._check_feature("differential tristate", pin, attrs,
 634                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 635         m = Module()
 636         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 637         for bit in range(pin.width):
 638             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 639                 i_T=t,
 640                 i_I=o[bit],
 641                 o_O=port.p[bit],
 642             )
 643         return m
 644
 645     def get_diff_input_output(self, pin, port, attrs, invert):
 646         self._check_feature("differential input/output", pin, attrs,
 647                             valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
 648         m = Module()
 649         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 650         for bit in range(pin.width):
 651             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 652                 i_T=t,
 653                 i_I=o[bit],
 654                 o_O=i[bit],
 655                 io_B=port.p[bit],
 656             )
 657         return m
 658
 659     # CDC primitives are not currently specialized for ECP5.
 660     # While Diamond supports false path constraints; nextpnr-ecp5 does not.