nmigen/vendor/lattice_ice40.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..lib.cdc import ResetSynchronizer
   5 from ..build import *
   6
   7
   8 __all__ = ["LatticeICE40Platform"]
   9
  10
  11 class LatticeICE40Platform(TemplatedPlatform):
  12     """
  13     IceStorm toolchain
  14     ------------------
  15
  16     Required tools:
  17         * ``yosys``
  18         * ``nextpnr-ice40``
  19         * ``icepack``
  20
  21     The environment is populated by running the script specified in the environment variable
  22     ``NMIGEN_ENV_IceStorm``, if present.
  23
  24     Available overrides:
  25         * ``verbose``: enables logging of informational messages to standard error.
  26         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  27         * ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
  28         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  29         * ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
  30         * ``yosys_opts``: adds extra options for ``yosys``.
  31         * ``nextpnr_opts``: adds extra options for ``nextpnr-ice40``.
  32         * ``add_pre_pack``: inserts commands at the end in pre-pack Python script.
  33         * ``add_constraints``: inserts commands at the end in the PCF file.
  34
  35     Build products:
  36         * ``{{name}}.rpt``: Yosys log.
  37         * ``{{name}}.json``: synthesized RTL.
  38         * ``{{name}}.tim``: nextpnr log.
  39         * ``{{name}}.asc``: ASCII bitstream.
  40         * ``{{name}}.bin``: binary bitstream.
  41
  42     iCECube2 toolchain
  43     ------------------
  44
  45     This toolchain comes in two variants: ``LSE-iCECube2`` and ``Synplify-iCECube2``.
  46
  47     Required tools:
  48         * iCECube2 toolchain
  49         * ``tclsh``
  50
  51     The environment is populated by setting the necessary environment variables based on
  52     ``NMIGEN_ENV_iCECube2``, which must point to the root of the iCECube2 installation, and
  53     is required.
  54
  55     Available overrides:
  56         * ``verbose``: enables logging of informational messages to standard error.
  57         * ``lse_opts``: adds options for LSE.
  58         * ``script_after_add``: inserts commands after ``add_file`` in Synplify Tcl script.
  59         * ``script_after_options``: inserts commands after ``set_option`` in Synplify Tcl script.
  60         * ``add_constraints``: inserts commands in SDC file.
  61         * ``script_after_flow``: inserts commands after ``run_sbt_backend_auto`` in SBT
  62           Tcl script.
  63
  64     Build products:
  65         * ``{{name}}_lse.log`` (LSE) or ``{{name}}_design/{{name}}.htm`` (Synplify): synthesis log.
  66         * ``sbt/outputs/router/{{name}}_timing.rpt``: timing report.
  67         * ``{{name}}.edf``: EDIF netlist.
  68         * ``{{name}}.bin``: binary bitstream.
  69     """
  70
  71     toolchain = None # selected when creating platform
  72
  73     device  = abstractproperty()
  74     package = abstractproperty()
  75
  76     # IceStorm templates
  77
  78     _nextpnr_device_options = {
  79         "iCE40LP384": "--lp384",
  80         "iCE40LP1K":  "--lp1k",
  81         "iCE40LP4K":  "--lp8k",
  82         "iCE40LP8K":  "--lp8k",
  83         "iCE40HX1K":  "--hx1k",
  84         "iCE40HX4K":  "--hx8k",
  85         "iCE40HX8K":  "--hx8k",
  86         "iCE40UP5K":  "--up5k",
  87         "iCE40UP3K":  "--up5k",
  88         "iCE5LP4K":   "--u4k",
  89         "iCE5LP2K":   "--u4k",
  90         "iCE5LP1K":   "--u4k",
  91     }
  92     _nextpnr_package_options = {
  93         "iCE40LP4K":  ":4k",
  94         "iCE40HX4K":  ":4k",
  95         "iCE40UP3K":  "",
  96         "iCE5LP2K":   "",
  97         "iCE5LP1K":   "",
  98     }
  99
 100     _icestorm_required_tools = [
 101         "yosys",
 102         "nextpnr-ice40",
 103         "icepack",
 104     ]
 105     _icestorm_file_templates = {
 106         **TemplatedPlatform.build_script_templates,
 107         "{{name}}.il": r"""
 108             # {{autogenerated}}
 109             {{emit_rtlil()}}
 110         """,
 111         "{{name}}.debug.v": r"""
 112             /* {{autogenerated}} */
 113             {{emit_debug_verilog()}}
 114         """,
 115         "{{name}}.ys": r"""
 116             # {{autogenerated}}
 117             {% for file in platform.iter_extra_files(".v") -%}
 118                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
 119             {% endfor %}
 120             {% for file in platform.iter_extra_files(".sv") -%}
 121                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
 122             {% endfor %}
 123             {% for file in platform.iter_extra_files(".il") -%}
 124                 read_ilang {{file}}
 125             {% endfor %}
 126             read_ilang {{name}}.il
 127             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
 128             synth_ice40 {{get_override("synth_opts")|options}} -top {{name}}
 129             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
 130             write_json {{name}}.json
 131         """,
 132         "{{name}}.pcf": r"""
 133             # {{autogenerated}}
 134             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 135                 set_io {{port_name}} {{pin_name}}
 136             {% endfor %}
 137             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 138                 set_frequency {{net_signal|hierarchy(".")}} {{frequency/1000000}}
 139             {% endfor%}
 140             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 141         """,
 142     }
 143     _icestorm_command_templates = [
 144         r"""
 145         {{invoke_tool("yosys")}}
 146             {{quiet("-q")}}
 147             {{get_override("yosys_opts")|options}}
 148             -l {{name}}.rpt
 149             {{name}}.ys
 150         """,
 151         r"""
 152         {{invoke_tool("nextpnr-ice40")}}
 153             {{quiet("--quiet")}}
 154             {{get_override("nextpnr_opts")|options}}
 155             --log {{name}}.tim
 156             {{platform._nextpnr_device_options[platform.device]}}
 157             --package
 158                 {{platform.package|lower}}{{platform._nextpnr_package_options[platform.device]|
 159                                             default("")}}
 160             --json {{name}}.json
 161             --pcf {{name}}.pcf
 162             --asc {{name}}.asc
 163         """,
 164         r"""
 165         {{invoke_tool("icepack")}}
 166             {{verbose("-v")}}
 167             {{name}}.asc
 168             {{name}}.bin
 169         """
 170     ]
 171
 172     # iCECube2 templates
 173
 174     _icecube2_required_tools = [
 175         "synthesis",
 176         "synpwrap",
 177         "tclsh",
 178     ]
 179     _icecube2_file_templates = {
 180         **TemplatedPlatform.build_script_templates,
 181         "build_{{name}}.sh": r"""
 182             # {{autogenerated}}
 183             set -e{{verbose("x")}}
 184             if [ -n "${{platform._toolchain_env_var}}" ]; then
 185                 # LSE environment
 186                 export LD_LIBRARY_PATH=${{platform._toolchain_env_var}}/LSE/bin/lin64:$LD_LIBRARY_PATH
 187                 export PATH=${{platform._toolchain_env_var}}/LSE/bin/lin64:$PATH
 188                 export FOUNDRY=${{platform._toolchain_env_var}}/LSE
 189                 # Synplify environment
 190                 export LD_LIBRARY_PATH=${{platform._toolchain_env_var}}/sbt_backend/bin/linux/opt/synpwrap:$LD_LIBRARY_PATH
 191                 export PATH=${{platform._toolchain_env_var}}/sbt_backend/bin/linux/opt/synpwrap:$PATH
 192                 export SYNPLIFY_PATH=${{platform._toolchain_env_var}}/synpbase
 193                 # Common environment
 194                 export SBT_DIR=${{platform._toolchain_env_var}}/sbt_backend
 195             else
 196                 echo "Variable ${{platform._toolchain_env_var}} must be set" >&2; exit 1
 197             fi
 198             {{emit_commands("sh")}}
 199         """,
 200         "{{name}}.v": r"""
 201             /* {{autogenerated}} */
 202             {{emit_verilog()}}
 203         """,
 204         "{{name}}.debug.v": r"""
 205             /* {{autogenerated}} */
 206             {{emit_debug_verilog()}}
 207         """,
 208         "{{name}}_lse.prj": r"""
 209             # {{autogenerated}}
 210             -a SBT{{platform.family}}
 211             -d {{platform.device}}
 212             -t {{platform.package}}
 213             {{get_override("lse_opts")|options|default("# (lse_opts placeholder)")}}
 214             {% for file in platform.iter_extra_files(".v") -%}
 215                 -ver {{file}}
 216             {% endfor %}
 217             -ver {{name}}.v
 218             -sdc {{name}}.sdc
 219             -top {{name}}
 220             -output_edif {{name}}.edf
 221             -logfile {{name}}_lse.log
 222         """,
 223         "{{name}}_syn.prj": r"""
 224             # {{autogenerated}}
 225             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
 226                 add_file -verilog {{file|tcl_escape}}
 227             {% endfor %}
 228             add_file -verilog {{name}}.v
 229             add_file -constraint {{name}}.sdc
 230             {{get_override("script_after_add")|default("# (script_after_add placeholder)")}}
 231             impl -add {{name}}_design -type fpga
 232             set_option -technology SBT{{platform.family}}
 233             set_option -part {{platform.device}}
 234             set_option -package {{platform.package}}
 235             {{get_override("script_after_options")|default("# (script_after_options placeholder)")}}
 236             project -result_format edif
 237             project -result_file {{name}}.edf
 238             impl -active {{name}}_design
 239             project -run compile
 240             project -run map
 241             project -run fpga_mapper
 242             file copy -force -- {{name}}_design/{{name}}.edf {{name}}.edf
 243         """,
 244         "{{name}}.sdc": r"""
 245             # {{autogenerated}}
 246             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 247                 {% if port_signal is not none -%}
 248                     create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 249                 {% else -%}
 250                     create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 251                 {% endif %}
 252             {% endfor %}
 253             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 254         """,
 255         "{{name}}.tcl": r"""
 256             # {{autogenerated}}
 257             set device {{platform.device}}-{{platform.package}}
 258             set top_module {{name}}
 259             set proj_dir .
 260             set output_dir .
 261             set edif_file {{name}}
 262             set tool_options ":edifparser -y {{name}}.pcf"
 263             set sbt_root $::env(SBT_DIR)
 264             append sbt_tcl $sbt_root "/tcl/sbt_backend_synpl.tcl"
 265             source $sbt_tcl
 266             run_sbt_backend_auto $device $top_module $proj_dir $output_dir $tool_options $edif_file
 267             {{get_override("script_after_file")|default("# (script_after_file placeholder)")}}
 268             file copy -force -- sbt/outputs/bitmap/{{name}}_bitmap.bin {{name}}.bin
 269             exit
 270         """,
 271         "{{name}}.pcf": r"""
 272             # {{autogenerated}}
 273             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 274                 set_io {{port_name}} {{pin_name}}
 275             {% endfor %}
 276         """,
 277     }
 278     _lse_icecube2_command_templates = [
 279         r"""synthesis -f {{name}}_lse.prj""",
 280         r"""tclsh {{name}}.tcl""",
 281     ]
 282     _synplify_icecube2_command_templates = [
 283         r"""synpwrap -prj {{name}}_syn.prj -log {{name}}_syn.log""",
 284         r"""tclsh {{name}}.tcl""",
 285     ]
 286
 287     # Common logic
 288
 289     def __init__(self, *, toolchain="IceStorm"):
 290         super().__init__()
 291
 292         assert toolchain in ("IceStorm", "LSE-iCECube2", "Synplify-iCECube2")
 293         self.toolchain = toolchain
 294
 295     @property
 296     def family(self):
 297         if self.device.startswith("iCE40"):
 298             return "iCE40"
 299         if self.device.startswith("iCE5"):
 300             return "iCE5"
 301         assert False
 302
 303     @property
 304     def _toolchain_env_var(self):
 305         if self.toolchain == "IceStorm":
 306             return f"NMIGEN_ENV_{self.toolchain}"
 307         if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
 308             return f"NMIGEN_ENV_iCECube2"
 309         assert False
 310
 311     @property
 312     def required_tools(self):
 313         if self.toolchain == "IceStorm":
 314             return self._icestorm_required_tools
 315         if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
 316             return self._icecube2_required_tools
 317         assert False
 318
 319     @property
 320     def file_templates(self):
 321         if self.toolchain == "IceStorm":
 322             return self._icestorm_file_templates
 323         if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
 324             return self._icecube2_file_templates
 325         assert False
 326
 327     @property
 328     def command_templates(self):
 329         if self.toolchain == "IceStorm":
 330             return self._icestorm_command_templates
 331         if self.toolchain == "LSE-iCECube2":
 332             return self._lse_icecube2_command_templates
 333         if self.toolchain == "Synplify-iCECube2":
 334             return self._synplify_icecube2_command_templates
 335         assert False
 336
 337     @property
 338     def default_clk_constraint(self):
 339         # Internal high-speed oscillator: 48 MHz / (2 ^ div)
 340         if self.default_clk == "SB_HFOSC":
 341             return Clock(48e6 / 2 ** self.hfosc_div)
 342         # Internal low-speed oscillator: 10 KHz
 343         elif self.default_clk == "SB_LFOSC":
 344             return Clock(10e3)
 345         # Otherwise, use the defined Clock resource.
 346         return super().default_clk_constraint
 347
 348     def create_missing_domain(self, name):
 349         # For unknown reasons (no errata was ever published, and no documentation mentions this
 350         # issue), iCE40 BRAMs read as zeroes for ~3 us after configuration and release of internal
 351         # global reset. Note that this is a *time-based* delay, generated purely by the internal
 352         # oscillator, which may not be observed nor influenced directly. For details, see links:
 353         #  * https://github.com/cliffordwolf/icestorm/issues/76#issuecomment-289270411
 354         #  * https://github.com/cliffordwolf/icotools/issues/2#issuecomment-299734673
 355         #
 356         # To handle this, it is necessary to have a global reset in any iCE40 design that may
 357         # potentially instantiate BRAMs, and assert this reset for >3 us after configuration.
 358         # (We add a margin of 5x to allow for PVT variation.) If the board includes a dedicated
 359         # reset line, this line is ORed with the power on reset.
 360         #
 361         # If an internal oscillator is selected as the default clock source, the power-on-reset
 362         # delay is increased to 100 us, since the oscillators are only stable after that long.
 363         #
 364         # The power-on reset timer counts up because the vendor tools do not support initialization
 365         # of flip-flops.
 366         if name == "sync" and self.default_clk is not None:
 367             m = Module()
 368
 369             # Internal high-speed clock: 6 MHz, 12 MHz, 24 MHz, or 48 MHz depending on the divider.
 370             if self.default_clk == "SB_HFOSC":
 371                 if not hasattr(self, "hfosc_div"):
 372                     raise ValueError("SB_HFOSC divider exponent (hfosc_div) must be an integer "
 373                                      "between 0 and 3")
 374                 if not isinstance(self.hfosc_div, int) or self.hfosc_div < 0 or self.hfosc_div > 3:
 375                     raise ValueError("SB_HFOSC divider exponent (hfosc_div) must be an integer "
 376                                      "between 0 and 3, not {!r}"
 377                                      .format(self.hfosc_div))
 378                 clk_i = Signal()
 379                 m.submodules += Instance("SB_HFOSC",
 380                                          i_CLKHFEN=1,
 381                                          i_CLKHFPU=1,
 382                                          p_CLKHF_DIV="0b{0:b}".format(self.hfosc_div),
 383                                          o_CLKHF=clk_i)
 384                 delay = int(100e-6 * self.default_clk_frequency)
 385             # Internal low-speed clock: 10 KHz.
 386             elif self.default_clk == "SB_LFOSC":
 387                 clk_i = Signal()
 388                 m.submodules += Instance("SB_LFOSC",
 389                                          i_CLKLFEN=1,
 390                                          i_CLKLFPU=1,
 391                                          o_CLKLF=clk_i)
 392                 delay = int(100e-6 * self.default_clk_frequency)
 393             # User-defined clock signal.
 394             else:
 395                 clk_i = self.request(self.default_clk).i
 396                 delay = int(15e-6 * self.default_clk_frequency)
 397
 398             if self.default_rst is not None:
 399                 rst_i = self.request(self.default_rst).i
 400             else:
 401                 rst_i = Const(0)
 402
 403             # Power-on-reset domain
 404             m.domains += ClockDomain("por", reset_less=True, local=True)
 405             timer = Signal(range(delay))
 406             ready = Signal()
 407             m.d.comb += ClockSignal("por").eq(clk_i)
 408             with m.If(timer == delay):
 409                 m.d.por += ready.eq(1)
 410             with m.Else():
 411                 m.d.por += timer.eq(timer + 1)
 412
 413             # Primary domain
 414             m.domains += ClockDomain("sync")
 415             m.d.comb += ClockSignal("sync").eq(clk_i)
 416             if self.default_rst is not None:
 417                 m.submodules.reset_sync = ResetSynchronizer(~ready | rst_i, domain="sync")
 418             else:
 419                 m.d.comb += ResetSignal("sync").eq(~ready)
 420
 421             return m
 422
 423     def should_skip_port_component(self, port, attrs, component):
 424         # On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
 425         # the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
 426         # between LP/HX and UP series:
 427         #  * for LP/HX, z=0 is DPxxB   (B is non-inverting, A is inverting)
 428         #  * for UP,    z=0 is IOB_xxA (A is non-inverting, B is inverting)
 429         if attrs.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT" and component == "n":
 430             return True
 431         return False
 432
 433     def _get_io_buffer(self, m, pin, port, attrs, *, i_invert=False, o_invert=False,
 434                        invert_lut=False):
 435         def get_dff(clk, d, q):
 436             m.submodules += Instance("$dff",
 437                 p_CLK_POLARITY=1,
 438                 p_WIDTH=len(d),
 439                 i_CLK=clk,
 440                 i_D=d,
 441                 o_Q=q)
 442
 443         def get_ineg(y, invert):
 444             if invert_lut:
 445                 a = Signal.like(y, name_suffix="_x{}".format(1 if invert else 0))
 446                 for bit in range(len(y)):
 447                     m.submodules += Instance("SB_LUT4",
 448                         p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
 449                         i_I0=a[bit],
 450                         i_I1=Const(0),
 451                         i_I2=Const(0),
 452                         i_I3=Const(0),
 453                         o_O=y[bit])
 454                 return a
 455             elif invert:
 456                 a = Signal.like(y, name_suffix="_n")
 457                 m.d.comb += y.eq(~a)
 458                 return a
 459             else:
 460                 return y
 461
 462         def get_oneg(a, invert):
 463             if invert_lut:
 464                 y = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
 465                 for bit in range(len(a)):
 466                     m.submodules += Instance("SB_LUT4",
 467                         p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
 468                         i_I0=a[bit],
 469                         i_I1=Const(0),
 470                         i_I2=Const(0),
 471                         i_I3=Const(0),
 472                         o_O=y[bit])
 473                 return y
 474             elif invert:
 475                 y = Signal.like(a, name_suffix="_n")
 476                 m.d.comb += y.eq(~a)
 477                 return y
 478             else:
 479                 return a
 480
 481         if "GLOBAL" in attrs:
 482             is_global_input = bool(attrs["GLOBAL"])
 483             del attrs["GLOBAL"]
 484         else:
 485             is_global_input = False
 486         assert not (is_global_input and i_invert)
 487
 488         if "i" in pin.dir:
 489             if pin.xdr < 2:
 490                 pin_i  = get_ineg(pin.i,  i_invert)
 491             elif pin.xdr == 2:
 492                 pin_i0 = get_ineg(pin.i0, i_invert)
 493                 pin_i1 = get_ineg(pin.i1, i_invert)
 494         if "o" in pin.dir:
 495             if pin.xdr < 2:
 496                 pin_o  = get_oneg(pin.o,  o_invert)
 497             elif pin.xdr == 2:
 498                 pin_o0 = get_oneg(pin.o0, o_invert)
 499                 pin_o1 = get_oneg(pin.o1, o_invert)
 500
 501         if "i" in pin.dir and pin.xdr == 2:
 502             i0_ff = Signal.like(pin_i0, name_suffix="_ff")
 503             i1_ff = Signal.like(pin_i1, name_suffix="_ff")
 504             get_dff(pin.i_clk, i0_ff, pin_i0)
 505             get_dff(pin.i_clk, i1_ff, pin_i1)
 506         if "o" in pin.dir and pin.xdr == 2:
 507             o1_ff = Signal.like(pin_o1, name_suffix="_ff")
 508             get_dff(pin.o_clk, pin_o1, o1_ff)
 509
 510         for bit in range(len(port)):
 511             io_args = [
 512                 ("io", "PACKAGE_PIN", port[bit]),
 513                 *(("p", key, value) for key, value in attrs.items()),
 514             ]
 515
 516             if "i" not in pin.dir:
 517                 # If no input pin is requested, it is important to use a non-registered input pin
 518                 # type, because an output-only pin would not have an input clock, and if its input
 519                 # is configured as registered, this would prevent a co-located input-capable pin
 520                 # from using an input clock.
 521                 i_type =     0b01 # PIN_INPUT
 522             elif pin.xdr == 0:
 523                 i_type =     0b01 # PIN_INPUT
 524             elif pin.xdr > 0:
 525                 i_type =     0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
 526             if "o" not in pin.dir:
 527                 o_type = 0b0000   # PIN_NO_OUTPUT
 528             elif pin.xdr == 0 and pin.dir == "o":
 529                 o_type = 0b0110   # PIN_OUTPUT
 530             elif pin.xdr == 0:
 531                 o_type = 0b1010   # PIN_OUTPUT_TRISTATE
 532             elif pin.xdr == 1 and pin.dir == "o":
 533                 o_type = 0b0101   # PIN_OUTPUT_REGISTERED
 534             elif pin.xdr == 1:
 535                 o_type = 0b1101   # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
 536             elif pin.xdr == 2 and pin.dir == "o":
 537                 o_type = 0b0100   # PIN_OUTPUT_DDR
 538             elif pin.xdr == 2:
 539                 o_type = 0b1100   # PIN_OUTPUT_DDR_ENABLE_REGISTERED
 540             io_args.append(("p", "PIN_TYPE", C((o_type << 2) | i_type, 6)))
 541
 542             if hasattr(pin, "i_clk"):
 543                 io_args.append(("i", "INPUT_CLK",  pin.i_clk))
 544             if hasattr(pin, "o_clk"):
 545                 io_args.append(("i", "OUTPUT_CLK", pin.o_clk))
 546
 547             if "i" in pin.dir:
 548                 if pin.xdr == 0 and is_global_input:
 549                     io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
 550                 elif pin.xdr < 2:
 551                     io_args.append(("o", "D_IN_0",  pin_i[bit]))
 552                 elif pin.xdr == 2:
 553                     # Re-register both inputs before they enter fabric. This increases hold time
 554                     # to an entire cycle, and adds one cycle of latency.
 555                     io_args.append(("o", "D_IN_0",  i0_ff[bit]))
 556                     io_args.append(("o", "D_IN_1",  i1_ff[bit]))
 557             if "o" in pin.dir:
 558                 if pin.xdr < 2:
 559                     io_args.append(("i", "D_OUT_0", pin_o[bit]))
 560                 elif pin.xdr == 2:
 561                     # Re-register negedge output after it leaves fabric. This increases setup time
 562                     # to an entire cycle, and doesn't add latency.
 563                     io_args.append(("i", "D_OUT_0", pin_o0[bit]))
 564                     io_args.append(("i", "D_OUT_1", o1_ff[bit]))
 565
 566             if pin.dir in ("oe", "io"):
 567                 io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
 568
 569             if is_global_input:
 570                 m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_GB_IO", *io_args)
 571             else:
 572                 m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_IO", *io_args)
 573
 574     def get_input(self, pin, port, attrs, invert):
 575         self._check_feature("single-ended input", pin, attrs,
 576                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 577         m = Module()
 578         self._get_io_buffer(m, pin, port.io, attrs, i_invert=invert)
 579         return m
 580
 581     def get_output(self, pin, port, attrs, invert):
 582         self._check_feature("single-ended output", pin, attrs,
 583                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 584         m = Module()
 585         self._get_io_buffer(m, pin, port.io, attrs, o_invert=invert)
 586         return m
 587
 588     def get_tristate(self, pin, port, attrs, invert):
 589         self._check_feature("single-ended tristate", pin, attrs,
 590                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 591         m = Module()
 592         self._get_io_buffer(m, pin, port.io, attrs, o_invert=invert)
 593         return m
 594
 595     def get_input_output(self, pin, port, attrs, invert):
 596         self._check_feature("single-ended input/output", pin, attrs,
 597                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 598         m = Module()
 599         self._get_io_buffer(m, pin, port.io, attrs, i_invert=invert, o_invert=invert)
 600         return m
 601
 602     def get_diff_input(self, pin, port, attrs, invert):
 603         self._check_feature("differential input", pin, attrs,
 604                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 605         m = Module()
 606         # See comment in should_skip_port_component above.
 607         self._get_io_buffer(m, pin, port.p, attrs, i_invert=invert)
 608         return m
 609
 610     def get_diff_output(self, pin, port, attrs, invert):
 611         self._check_feature("differential output", pin, attrs,
 612                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 613         m = Module()
 614         # Note that the non-inverting output pin is not driven the same way as a regular
 615         # output pin. The inverter introduces a delay, so for a non-inverting output pin,
 616         # an identical delay is introduced by instantiating a LUT. This makes the waveform
 617         # perfectly symmetric in the xdr=0 case.
 618         self._get_io_buffer(m, pin, port.p, attrs, o_invert=    invert, invert_lut=True)
 619         self._get_io_buffer(m, pin, port.n, attrs, o_invert=not invert, invert_lut=True)
 620         return m
 621
 622     # Tristate bidirectional buffers are not supported on iCE40 because it requires external
 623     # termination, which is different for differential pins configured as inputs and outputs.
 624
 625     # CDC primitives are not currently specialized for iCE40. It is not known if iCECube2 supports
 626     # the necessary attributes; nextpnr-ice40 does not.