nmigen/vendor/lattice_ice40.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeICE40Platform"]
   8
   9
  10 class LatticeICE40Platform(TemplatedPlatform):
  11     """
  12     Required tools:
  13         * ``yosys``
  14         * ``nextpnr-ice40``
  15         * ``icepack``
  16
  17     Available overrides:
  18         * ``verbose``: enables logging of informational messages to standard error.
  19         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  20         * ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
  21         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  22         * ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
  23         * ``yosys_opts``: adds extra options for Yosys.
  24         * ``nextpnr_opts``: adds extra and overrides default options (``--placer heap``)
  25           for nextpnr.
  26
  27     Build products:
  28         * ``{{name}}.rpt``: Yosys log.
  29         * ``{{name}}.json``: synthesized RTL.
  30         * ``{{name}}.tim``: nextpnr log.
  31         * ``{{name}}.asc``: ASCII bitstream.
  32         * ``{{name}}.bin``: binary bitstream.
  33     """
  34
  35     device  = abstractproperty()
  36     package = abstractproperty()
  37
  38     _nextpnr_device_options = {
  39         "iCE40LP384": "--lp384",
  40         "iCE40LP1K":  "--lp1k",
  41         "iCE40LP4K":  "--lp8k",
  42         "iCE40LP8K":  "--lp8k",
  43         "iCE40HX1K":  "--hx1k",
  44         "iCE40HX4K":  "--hx8k",
  45         "iCE40HX8K":  "--hx8k",
  46         "iCE40UP5K":  "--up5k",
  47         "iCE5LP4K":   "--u4k",
  48     }
  49     _nextpnr_package_options = {
  50         "iCE40LP4K":  ":4k",
  51         "iCE40HX4K":  ":4k",
  52     }
  53
  54     file_templates = {
  55         **TemplatedPlatform.build_script_templates,
  56         "{{name}}.il": r"""
  57             # {{autogenerated}}
  58             {{emit_design("rtlil")}}
  59         """,
  60         "{{name}}.ys": r"""
  61             # {{autogenerated}}
  62             {% for file in platform.iter_extra_files(".v") -%}
  63                 read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
  64             {% endfor %}
  65             {% for file in platform.iter_extra_files(".sv") -%}
  66                 read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
  67             {% endfor %}
  68             read_ilang {{name}}.il
  69             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
  70             synth_ice40 {{get_override("synth_opts")|join(" ")}} -top {{name}}
  71             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
  72             write_json {{name}}.json
  73         """,
  74         "{{name}}.pcf": r"""
  75             # {{autogenerated}}
  76             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
  77                 set_io {{port_name}} {{pin_name}}
  78             {% endfor %}
  79         """,
  80         "{{name}}_pre_pack.py": r"""
  81             # {{autogenerated}}
  82             {% for signal, frequency in platform.iter_clock_constraints() -%}
  83             {# Clock in MHz #}
  84             ctx.addClock("{{signal.name}}", {{frequency/1000000}})
  85             {% endfor%}
  86         """,
  87     }
  88     command_templates = [
  89         r"""
  90         {{get_tool("yosys")}}
  91             {{quiet("-q")}}
  92             {{get_override("yosys_opts")|join(" ")}}
  93             -l {{name}}.rpt
  94             {{name}}.ys
  95         """,
  96         r"""
  97         {{get_tool("nextpnr-ice40")}}
  98             {{quiet("--quiet")}}
  99             {{get_override("nextpnr_opts")|default(["--placer","heap"])|join(" ")}}
 100             --log {{name}}.tim
 101             {{platform._nextpnr_device_options[platform.device]}}
 102             --package
 103                 {{platform.package|lower}}{{platform._nextpnr_package_options[platform.device]}}
 104             --json {{name}}.json
 105             --pcf {{name}}.pcf
 106             --pre-pack {{name}}_pre_pack.py
 107             --asc {{name}}.asc
 108         """,
 109         r"""
 110         {{get_tool("icepack")}}
 111             {{verbose("-v")}}
 112             {{name}}.asc
 113             {{name}}.bin
 114         """
 115     ]
 116
 117     def should_skip_port_component(self, port, attrs, component):
 118         # On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
 119         # the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
 120         # between LP/HX and UP series:
 121         #  * for LP/HX, z=0 is DPxxB   (B is non-inverting, A is inverting)
 122         #  * for UP,    z=0 is IOB_xxA (A is non-inverting, B is inverting)
 123         if attrs.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT" and component == "n":
 124             return True
 125         return False
 126
 127     def _get_io_buffer(self, m, pin, port, attrs, i_invert=None, o_invert=None):
 128         def get_dff(clk, d, q):
 129             m.submodules += Instance("$dff",
 130                 p_CLK_POLARITY=1,
 131                 p_WIDTH=len(d),
 132                 i_CLK=clk,
 133                 i_D=d,
 134                 o_Q=q)
 135
 136         def get_ixor(y, invert):
 137             if invert is None:
 138                 return y
 139             else:
 140                 a = Signal.like(y, name_suffix="_x{}".format(1 if invert else 0))
 141                 for bit in range(len(y)):
 142                     m.submodules += Instance("SB_LUT4",
 143                         p_LUT_INIT=0b01 if invert else 0b10,
 144                         i_I0=a[bit],
 145                         i_I1=Const(0),
 146                         i_I2=Const(0),
 147                         i_I3=Const(0),
 148                         o_O=y[bit])
 149                 return a
 150
 151         def get_oxor(a, invert):
 152             if invert is None:
 153                 return a
 154             else:
 155                 y = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
 156                 for bit in range(len(a)):
 157                     m.submodules += Instance("SB_LUT4",
 158                         p_LUT_INIT=0b01 if invert else 0b10,
 159                         i_I0=a[bit],
 160                         i_I1=Const(0),
 161                         i_I2=Const(0),
 162                         i_I3=Const(0),
 163                         o_O=y[bit])
 164                 return y
 165
 166         if "GLOBAL" in attrs:
 167             is_global_input = bool(attrs["GLOBAL"])
 168             del attrs["GLOBAL"]
 169         else:
 170             is_global_input = False
 171         assert not (is_global_input and i_invert)
 172
 173         if "i" in pin.dir:
 174             if pin.xdr < 2:
 175                 pin_i  = get_ixor(pin.i,  i_invert)
 176             elif pin.xdr == 2:
 177                 pin_i0 = get_ixor(pin.i0, i_invert)
 178                 pin_i1 = get_ixor(pin.i1, i_invert)
 179         if "o" in pin.dir:
 180             if pin.xdr < 2:
 181                 pin_o  = get_oxor(pin.o,  o_invert)
 182             elif pin.xdr == 2:
 183                 pin_o0 = get_oxor(pin.o0, o_invert)
 184                 pin_o1 = get_oxor(pin.o1, o_invert)
 185
 186         if "i" in pin.dir and pin.xdr == 2:
 187             i0_ff = Signal.like(pin_i0, name_suffix="_ff")
 188             i1_ff = Signal.like(pin_i1, name_suffix="_ff")
 189             get_dff(pin.i_clk, i0_ff, pin_i0)
 190             get_dff(pin.i_clk, i1_ff, pin_i1)
 191         if "o" in pin.dir and pin.xdr == 2:
 192             o1_ff = Signal.like(pin_o1, name_suffix="_ff")
 193             get_dff(pin.o_clk, pin_o1, o1_ff)
 194
 195         for bit in range(len(port)):
 196             io_args = [
 197                 ("io", "PACKAGE_PIN", port[bit]),
 198                 *(("p", key, value) for key, value in attrs.items()),
 199             ]
 200
 201             if "i" not in pin.dir:
 202                 i_type =     0b00 # PIN_NO_INPUT aka PIN_INPUT_REGISTERED
 203             elif pin.xdr == 0:
 204                 i_type =     0b01 # PIN_INPUT
 205             elif pin.xdr > 0:
 206                 i_type =     0b00 # PIN_INPUT_REGISTERED
 207             if "o" not in pin.dir:
 208                 o_type = 0b0000   # PIN_NO_OUTPUT
 209             elif pin.xdr == 0 and pin.dir == "o":
 210                 o_type = 0b0110   # PIN_OUTPUT
 211             elif pin.xdr == 0:
 212                 o_type = 0b1010   # PIN_OUTPUT_TRISTATE
 213             elif pin.xdr == 1 and pin.dir == "o":
 214                 o_type = 0b0101   # PIN_OUTPUT_REGISTERED
 215             elif pin.xdr == 1:
 216                 o_type = 0b1101   # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
 217             elif pin.xdr == 2 and pin.dir == "o":
 218                 o_type = 0b0100   # PIN_OUTPUT_DDR
 219             elif pin.xdr == 2:
 220                 o_type = 0b1100   # PIN_OUTPUT_DDR_ENABLE_REGISTERED
 221             io_args.append(("p", "PIN_TYPE", (o_type << 2) | i_type))
 222
 223             if hasattr(pin, "i_clk"):
 224                 io_args.append(("i", "INPUT_CLK",  pin.i_clk))
 225             if hasattr(pin, "o_clk"):
 226                 io_args.append(("i", "OUTPUT_CLK", pin.o_clk))
 227
 228             if "i" in pin.dir:
 229                 if pin.xdr == 0 and is_global_input:
 230                     io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
 231                 elif pin.xdr < 2:
 232                     io_args.append(("o", "D_IN_0",  pin_i[bit]))
 233                 elif pin.xdr == 2:
 234                     # Re-register both inputs before they enter fabric. This increases hold time
 235                     # to an entire cycle, and adds one cycle of latency.
 236                     io_args.append(("o", "D_IN_0",  i0_ff))
 237                     io_args.append(("o", "D_IN_1",  i1_ff))
 238             if "o" in pin.dir:
 239                 if pin.xdr < 2:
 240                     io_args.append(("i", "D_OUT_0", pin_o[bit]))
 241                 elif pin.xdr == 2:
 242                     # Re-register negedge output after it leaves fabric. This increases setup time
 243                     # to an entire cycle, and doesn't add latency.
 244                     io_args.append(("i", "D_OUT_0", pin_o0[bit]))
 245                     io_args.append(("i", "D_OUT_1", o1_ff))
 246
 247             if pin.dir in ("oe", "io"):
 248                 io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
 249
 250             if is_global_input:
 251                 m.submodules += Instance("SB_GB_IO", *io_args)
 252             else:
 253                 m.submodules += Instance("SB_IO", *io_args)
 254
 255     def get_input(self, pin, port, attrs, invert):
 256         self._check_feature("single-ended input", pin, attrs,
 257                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 258         m = Module()
 259         self._get_io_buffer(m, pin, port, attrs, i_invert=True if invert else None)
 260         return m
 261
 262     def get_output(self, pin, port, attrs, invert):
 263         self._check_feature("single-ended output", pin, attrs,
 264                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 265         m = Module()
 266         self._get_io_buffer(m, pin, port, attrs, o_invert=True if invert else None)
 267         return m
 268
 269     def get_tristate(self, pin, port, attrs, invert):
 270         self._check_feature("single-ended tristate", pin, attrs,
 271                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 272         m = Module()
 273         self._get_io_buffer(m, pin, port, attrs, o_invert=True if invert else None)
 274         return m
 275
 276     def get_input_output(self, pin, port, attrs, invert):
 277         self._check_feature("single-ended input/output", pin, attrs,
 278                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 279         m = Module()
 280         self._get_io_buffer(m, pin, port, attrs, i_invert=True if invert else None,
 281                                                  o_invert=True if invert else None)
 282         return m
 283
 284     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 285         self._check_feature("differential input", pin, attrs,
 286                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 287         m = Module()
 288         # See comment in should_skip_port_component above.
 289         self._get_io_buffer(m, pin, p_port, attrs, i_invert=True if invert else None)
 290         return m
 291
 292     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 293         self._check_feature("differential output", pin, attrs,
 294                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 295         m = Module()
 296         # Note that the non-inverting output pin is not driven the same way as a regular
 297         # output pin. The inverter introduces a delay, so for a non-inverting output pin,
 298         # an identical delay is introduced by instantiating a LUT. This makes the waveform
 299         # perfectly symmetric in the xdr=0 case.
 300         self._get_io_buffer(m, pin, p_port, attrs, o_invert=invert)
 301         self._get_io_buffer(m, pin, n_port, attrs, o_invert=not invert)
 302         return m
 303
 304     # Tristate and bidirectional buffers are not supported on iCE40 because it requires external
 305     # termination, which is incompatible for input and output differential I/Os.