nmigen/vendor/lattice_machxo_2_3l.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeMachXO2Platform", "LatticeMachXO3LPlatform"]
   8
   9
  10 # MachXO2 and MachXO3L primitives are the same. Handle both using
  11 # one class and expose user-aliases for convenience.
  12 class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
  13     """
  14     Required tools:
  15         * ``pnmainc``
  16         * ``ddtcmd``
  17
  18     The environment is populated by running the script specified in the environment variable
  19     ``NMIGEN_ENV_Diamond``, if present. On Linux, diamond_env as provided by Diamond
  20     itself is a good candidate. On Windows, the following script (named ``diamond_env.bat``,
  21     for instance) is known to work::
  22
  23         @echo off
  24         set PATH=C:\\lscc\\diamond\\%DIAMOND_VERSION%\\bin\\nt64;%PATH%
  25
  26     Available overrides:
  27         * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
  28         * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
  29         * ``add_preferences``: inserts commands at the end of the LPF file.
  30         * ``add_constraints``: inserts commands at the end of the XDC file.
  31
  32     Build products:
  33         * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
  34         * ``{{name}}.jed``: JEDEC fuse file.
  35         * ``{{name}}.bit``: binary bitstream.
  36         * ``{{name}}.svf``: JTAG programming vector for FLASH programming.
  37         * ``{{name}}_flash.svf``: JTAG programming vector for FLASH programming.
  38         * ``{{name}}_sram.svf``: JTAG programming vector for SRAM programming.
  39     """
  40
  41     toolchain = "Diamond"
  42
  43     device  = abstractproperty()
  44     package = abstractproperty()
  45     speed   = abstractproperty()
  46     grade   = "C" # [C]ommercial, [I]ndustrial
  47
  48     required_tools = [
  49         "pnmainc",
  50         "ddtcmd"
  51     ]
  52     file_templates = {
  53         **TemplatedPlatform.build_script_templates,
  54         "build_{{name}}.sh": r"""
  55             # {{autogenerated}}
  56             set -e{{verbose("x")}}
  57             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
  58             if [ -n "${{platform._toolchain_env_var}}" ]; then
  59                 bindir=$(dirname "${{platform._toolchain_env_var}}")
  60                 . "${{platform._toolchain_env_var}}"
  61             fi
  62             {{emit_commands("sh")}}
  63         """,
  64         "{{name}}.v": r"""
  65             /* {{autogenerated}} */
  66             {{emit_verilog()}}
  67         """,
  68         "{{name}}.debug.v": r"""
  69             /* {{autogenerated}} */
  70             {{emit_debug_verilog()}}
  71         """,
  72         "{{name}}.tcl": r"""
  73             prj_project new -name {{name}} -impl impl -impl_dir {{name}}_impl \
  74                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
  75                 -lpf {{name}}.lpf \
  76                 -synthesis synplify
  77             {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
  78                 prj_src add {{file|tcl_escape}}
  79             {% endfor %}
  80             prj_src add {{name}}.v
  81             prj_impl option top {{name}}
  82             prj_src add {{name}}.sdc
  83             {{get_override("script_project")|default("# (script_project placeholder)")}}
  84             prj_project save
  85             prj_run Synthesis -impl impl
  86             prj_run Translate -impl impl
  87             prj_run Map -impl impl
  88             prj_run PAR -impl impl
  89             prj_run Export -impl impl -task Bitgen
  90             prj_run Export -impl impl -task Jedecgen
  91             {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
  92         """,
  93         "{{name}}.lpf": r"""
  94             # {{autogenerated}}
  95             BLOCK ASYNCPATHS;
  96             BLOCK RESETPATHS;
  97             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
  98                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
  99                 {% if attrs -%}
 100                 IOBUF PORT "{{port_name}}"
 101                     {%- for key, value in attrs.items() %} {{key}}={{value}}{% endfor %};
 102                 {% endif %}
 103             {% endfor %}
 104             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 105         """,
 106         "{{name}}.sdc": r"""
 107             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 108                 {% if port_signal is not none -%}
 109                     create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 110                 {% else -%}
 111                     create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 112                 {% endif %}
 113             {% endfor %}
 114             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 115         """,
 116     }
 117     command_templates = [
 118         # These don't have any usable command-line option overrides.
 119         r"""
 120         {{invoke_tool("pnmainc")}}
 121             {{name}}.tcl
 122         """,
 123         r"""
 124         {{invoke_tool("ddtcmd")}}
 125             -oft -bit
 126             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
 127         """,
 128         r"""
 129         {{invoke_tool("ddtcmd")}}
 130             -oft -jed
 131             -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}}
 132             -if {{name}}_impl/{{name}}_impl.jed -of {{name}}.jed
 133         """,
 134         r"""
 135         {{invoke_tool("ddtcmd")}}
 136             -oft -svfsingle -revd -op "FLASH Erase,Program,Verify"
 137             -if {{name}}_impl/{{name}}_impl.jed -of {{name}}_flash.svf
 138         """,
 139         # TODO(nmigen-0.4): remove
 140         r"""
 141         {% if syntax == "bat" -%}
 142         copy {{name}}_flash.svf {{name}}.svf
 143         {% else -%}
 144         cp {{name}}_flash.svf {{name}}.svf
 145         {% endif %}
 146         """,
 147         r"""
 148         {{invoke_tool("ddtcmd")}}
 149             -oft -svfsingle -revd -op "SRAM Fast Program"
 150             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}_sram.svf
 151         """,
 152     ]
 153
 154     def create_missing_domain(self, name):
 155         # Lattice MachXO2/MachXO3L devices have two global set/reset signals: PUR, which is driven at
 156         # startup by the configuration logic and unconditionally resets every storage element,
 157         # and GSR, which is driven by user logic and each storage element may be configured as
 158         # affected or unaffected by GSR. PUR is purely asynchronous, so even though it is
 159         # a low-skew global network, its deassertion may violate a setup/hold constraint with
 160         # relation to a user clock. To avoid this, a GSR/SGSR instance should be driven
 161         # synchronized to user clock.
 162         if name == "sync" and self.default_clk is not None:
 163             clk_i = self.request(self.default_clk).i
 164             if self.default_rst is not None:
 165                 rst_i = self.request(self.default_rst).i
 166             else:
 167                 rst_i = Const(0)
 168
 169             gsr0 = Signal()
 170             gsr1 = Signal()
 171             m = Module()
 172             # There is no end-of-startup signal on MachXO2/MachXO3L, but PUR is released after IOB
 173             # enable, so a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
 174             m.submodules += [
 175                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
 176                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
 177                 # Although we already synchronize the reset input to user clock, SGSR has dedicated
 178                 # clock routing to the center of the FPGA; use that just in case it turns out to be
 179                 # more reliable. (None of this is documented.)
 180                 Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
 181             ]
 182             # GSR implicitly connects to every appropriate storage element. As such, the sync
 183             # domain is reset-less; domains driven by other clocks would need to have dedicated
 184             # reset circuitry or otherwise meet setup/hold constraints on their own.
 185             m.domains += ClockDomain("sync", reset_less=True)
 186             m.d.comb += ClockSignal("sync").eq(clk_i)
 187             return m
 188
 189     _single_ended_io_types = [
 190         "PCI33", "LVTTL33", "LVCMOS33", "LVCMOS25", "LVCMOS18", "LVCMOS15", "LVCMOS12",
 191         "LVCMOS25R33", "LVCMOS18R33", "LVCMOS18R25", "LVCMOS15R33", "LVCMOS15R25", "LVCMOS12R33",
 192         "LVCMOS12R25", "LVCMOS10R33", "LVCMOS10R25", "SSTL25_I", "SSTL25_II", "SSTL18_I",
 193         "SSTL18_II", "HSTL18_I", "HSTL18_II",
 194     ]
 195     _differential_io_types = [
 196         "LVDS25", "LVDS25E", "RSDS25", "RSDS25E", "BLVDS25", "BLVDS25E", "MLVDS25", "MLVDS25E",
 197         "LVPECL33", "LVPECL33E", "SSTL25D_I", "SSTL25D_II", "SSTL18D_I", "SSTL18D_II",
 198         "HSTL18D_I", "HSTL18D_II", "LVTTL33D", "LVCMOS33D", "LVCMOS25D", "LVCMOS18D", "LVCMOS15D",
 199         "LVCMOS12D", "MIPI",
 200     ]
 201
 202     def should_skip_port_component(self, port, attrs, component):
 203         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 204         # the PIOA or PIOC location, which is always the non-inverting pin.
 205         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 206             return True
 207         return False
 208
 209     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 210         def get_ireg(clk, d, q):
 211             for bit in range(len(q)):
 212                 m.submodules += Instance("IFS1P3DX",
 213                     i_SCLK=clk,
 214                     i_SP=Const(1),
 215                     i_CD=Const(0),
 216                     i_D=d[bit],
 217                     o_Q=q[bit]
 218                 )
 219
 220         def get_oreg(clk, d, q):
 221             for bit in range(len(q)):
 222                 m.submodules += Instance("OFS1P3DX",
 223                     i_SCLK=clk,
 224                     i_SP=Const(1),
 225                     i_CD=Const(0),
 226                     i_D=d[bit],
 227                     o_Q=q[bit]
 228                 )
 229
 230         def get_iddr(sclk, d, q0, q1):
 231             for bit in range(len(d)):
 232                 m.submodules += Instance("IDDRXE",
 233                     i_SCLK=sclk,
 234                     i_RST=Const(0),
 235                     i_D=d[bit],
 236                     o_Q0=q0[bit], o_Q1=q1[bit]
 237                 )
 238
 239         def get_oddr(sclk, d0, d1, q):
 240             for bit in range(len(q)):
 241                 m.submodules += Instance("ODDRXE",
 242                     i_SCLK=sclk,
 243                     i_RST=Const(0),
 244                     i_D0=d0[bit], i_D1=d1[bit],
 245                     o_Q=q[bit]
 246                 )
 247
 248         def get_ineg(z, invert):
 249             if invert:
 250                 a = Signal.like(z, name_suffix="_n")
 251                 m.d.comb += z.eq(~a)
 252                 return a
 253             else:
 254                 return z
 255
 256         def get_oneg(a, invert):
 257             if invert:
 258                 z = Signal.like(a, name_suffix="_n")
 259                 m.d.comb += z.eq(~a)
 260                 return z
 261             else:
 262                 return a
 263
 264         if "i" in pin.dir:
 265             if pin.xdr < 2:
 266                 pin_i  = get_ineg(pin.i,  i_invert)
 267             elif pin.xdr == 2:
 268                 pin_i0 = get_ineg(pin.i0, i_invert)
 269                 pin_i1 = get_ineg(pin.i1, i_invert)
 270         if "o" in pin.dir:
 271             if pin.xdr < 2:
 272                 pin_o  = get_oneg(pin.o,  o_invert)
 273             elif pin.xdr == 2:
 274                 pin_o0 = get_oneg(pin.o0, o_invert)
 275                 pin_o1 = get_oneg(pin.o1, o_invert)
 276
 277         i = o = t = None
 278         if "i" in pin.dir:
 279             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 280         if "o" in pin.dir:
 281             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 282         if pin.dir in ("oe", "io"):
 283             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 284
 285         if pin.xdr == 0:
 286             if "i" in pin.dir:
 287                 i = pin_i
 288             if "o" in pin.dir:
 289                 o = pin_o
 290             if pin.dir in ("oe", "io"):
 291                 t = ~pin.oe
 292         elif pin.xdr == 1:
 293             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 294             if "i" in pin.dir:
 295                 get_ireg(pin.i_clk, i, pin_i)
 296             if "o" in pin.dir:
 297                 get_oreg(pin.o_clk, pin_o, o)
 298             if pin.dir in ("oe", "io"):
 299                 get_oreg(pin.o_clk, ~pin.oe, t)
 300         elif pin.xdr == 2:
 301             if "i" in pin.dir:
 302                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 303             if "o" in pin.dir:
 304                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 305             if pin.dir in ("oe", "io"):
 306                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 307                 # It is not clear what is the recommended set of primitives for this task.
 308                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 309                 get_oreg(pin.o_clk, ~pin.oe, t)
 310         else:
 311             assert False
 312
 313         return (i, o, t)
 314
 315     def get_input(self, pin, port, attrs, invert):
 316         self._check_feature("single-ended input", pin, attrs,
 317                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 318         m = Module()
 319         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 320         for bit in range(len(port)):
 321             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 322                 i_I=port.io[bit],
 323                 o_O=i[bit]
 324             )
 325         return m
 326
 327     def get_output(self, pin, port, attrs, invert):
 328         self._check_feature("single-ended output", pin, attrs,
 329                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 330         m = Module()
 331         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 332         for bit in range(len(port)):
 333             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 334                 i_I=o[bit],
 335                 o_O=port.io[bit]
 336             )
 337         return m
 338
 339     def get_tristate(self, pin, port, attrs, invert):
 340         self._check_feature("single-ended tristate", pin, attrs,
 341                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 342         m = Module()
 343         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 344         for bit in range(len(port)):
 345             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 346                 i_T=t,
 347                 i_I=o[bit],
 348                 o_O=port.io[bit]
 349             )
 350         return m
 351
 352     def get_input_output(self, pin, port, attrs, invert):
 353         self._check_feature("single-ended input/output", pin, attrs,
 354                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 355         m = Module()
 356         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 357         for bit in range(len(port)):
 358             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 359                 i_T=t,
 360                 i_I=o[bit],
 361                 o_O=i[bit],
 362                 io_B=port.io[bit]
 363             )
 364         return m
 365
 366     def get_diff_input(self, pin, port, attrs, invert):
 367         self._check_feature("differential input", pin, attrs,
 368                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 369         m = Module()
 370         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 371         for bit in range(pin.width):
 372             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 373                 i_I=port.p[bit],
 374                 o_O=i[bit]
 375             )
 376         return m
 377
 378     def get_diff_output(self, pin, port, attrs, invert):
 379         self._check_feature("differential output", pin, attrs,
 380                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 381         m = Module()
 382         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 383         for bit in range(pin.width):
 384             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 385                 i_I=o[bit],
 386                 o_O=port.p[bit],
 387             )
 388         return m
 389
 390     def get_diff_tristate(self, pin, port, attrs, invert):
 391         self._check_feature("differential tristate", pin, attrs,
 392                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 393         m = Module()
 394         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 395         for bit in range(pin.width):
 396             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 397                 i_T=t,
 398                 i_I=o[bit],
 399                 o_O=port.p[bit],
 400             )
 401         return m
 402
 403     def get_diff_input_output(self, pin, port, attrs, invert):
 404         self._check_feature("differential input/output", pin, attrs,
 405                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 406         m = Module()
 407         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 408         for bit in range(pin.width):
 409             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 410                 i_T=t,
 411                 i_I=o[bit],
 412                 o_O=i[bit],
 413                 io_B=port.p[bit],
 414             )
 415         return m
 416
 417     # CDC primitives are not currently specialized for MachXO2/MachXO3L.
 418
 419
 420 LatticeMachXO2Platform = LatticeMachXO2Or3LPlatform
 421 LatticeMachXO3LPlatform = LatticeMachXO2Or3LPlatform