nmigen/vendor/quicklogic.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..lib.cdc import ResetSynchronizer
   5 from ..build import *
   6
   7
   8 __all__ = ["QuicklogicPlatform"]
   9
  10
  11 class QuicklogicPlatform(TemplatedPlatform):
  12     """
  13     Symbiflow toolchain
  14     -------------------
  15     Required tools:
  16         * ``synth``
  17         * ``pack``
  18         * ``place``
  19         * ``route``
  20         * ``write_fasm``
  21         * ``write_bitstream``
  22     The environment is populated by running the script specified in the environment variable
  23     ``NMIGEN_ENV_Quicklogic``, if present.
  24     Available overrides:
  25         * ``add_constraints``: inserts commands in XDC file.
  26     """
  27
  28     device  = abstractproperty()
  29     part    = abstractproperty()
  30
  31     required_tools = [
  32         "synth",
  33         "pack",
  34         "place",
  35         "route",
  36         "write_fasm",
  37         "write_bitstream"
  38     ]
  39     file_templates = {
  40         **TemplatedPlatform.build_script_templates,
  41         "{{name}}.v": r"""
  42             /* {{autogenerated}} */
  43             {{emit_verilog()}}
  44         """,
  45         "{{name}}.debug.v": r"""
  46             /* {{autogenerated}} */
  47             {{emit_debug_verilog()}}
  48         """,
  49         "{{name}}.pcf": r"""
  50             # {{autogenerated}}
  51             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
  52                 set_io {{port_name}} {{pin_name}}
  53             {% endfor %}
  54         """,
  55         "{{name}}.xdc": r"""
  56             # {{autogenerated}}
  57             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
  58                 {% for attr_name, attr_value in attrs.items() -%}
  59                     set_property {{attr_name}} {{attr_value}} [get_ports {{port_name|tcl_escape}} }]
  60                 {% endfor %}
  61             {% endfor %}
  62             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
  63         """,
  64         "{{name}}.sdc": r"""
  65             # {{autogenerated}}
  66             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
  67                 {% if port_signal is not none -%}
  68                     create_clock -period {{100000000/frequency}} {{port_signal.name|ascii_escape}}
  69                 {% endif %}
  70             {% endfor %}
  71         """
  72     }
  73     command_templates = [
  74         r"""
  75         {{invoke_tool("synth")}}
  76             -t {{name}}
  77             -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
  78             -d {{platform.device}}
  79             -p {{name}}.pcf
  80             -P {{platform.part}}
  81             -x {{name}}.xdc
  82         """,
  83         r"""
  84         {{invoke_tool("pack")}}
  85             -e {{name}}.eblif
  86             -d {{platform.device}}
  87             -s {{name}}.sdc
  88         """,
  89         r"""
  90         {{invoke_tool("place")}}
  91             -e {{name}}.eblif
  92             -d {{platform.device}}
  93             -p {{name}}.pcf
  94             -n {{name}}.net
  95             -P {{platform.part}}
  96             -s {{name}}.sdc
  97         """,
  98         r"""
  99         {{invoke_tool("route")}}
 100             -e {{name}}.eblif
 101             -d {{platform.device}}
 102             -s {{name}}.sdc
 103         """,
 104         r"""
 105         {{invoke_tool("write_fasm")}}
 106             -e {{name}}.eblif
 107             -d {{platform.device}}
 108             -s {{name}}.sdc
 109         """,
 110         r"""
 111         {{invoke_tool("write_bitstream")}}
 112             -f {{name}}.fasm
 113             -d {{platform.device}}
 114             -P {{platform.part}}
 115             -b {{name}}.bit
 116         """
 117     ]
 118
 119     # Common logic
 120
 121     def __init__(self, *):
 122         super().__init__()
 123
 124     def add_clock_constraint(self, clock, frequency):
 125         super().add_clock_constraint(clock, frequency)
 126         clock.attrs["keep"] = "TRUE"