1 from abc
import abstractproperty
4 from ..lib
.cdc
import ResetSynchronizer
8 __all__
= ["QuicklogicPlatform"]
11 class QuicklogicPlatform(TemplatedPlatform
):
22 The environment is populated by running the script specified in the environment variable
23 ``NMIGEN_ENV_Quicklogic``, if present.
25 * ``add_constraints``: inserts commands in XDC file.
28 device
= abstractproperty()
29 part
= abstractproperty()
40 **TemplatedPlatform
.build_script_templates
,
42 /* {{autogenerated}} */
45 "{{name}}.debug.v": r
"""
46 /* {{autogenerated}} */
47 {{emit_debug_verilog()}}
51 {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
52 set_io {{port_name}} {{pin_name}}
57 {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
58 {% for attr_name, attr_value in attrs.items() -%}
59 set_property {{attr_name}} {{attr_value}} [get_ports {{port_name|tcl_escape}} }]
62 {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
66 {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
67 {% if port_signal is not none -%}
68 create_clock -period {{100000000/frequency}} {{port_signal.name|ascii_escape}}
75 {{invoke_tool("synth")}}
77 -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
78 -d {{platform.device}}
84 {{invoke_tool("pack")}}
86 -d {{platform.device}}
90 {{invoke_tool("place")}}
92 -d {{platform.device}}
99 {{invoke_tool("route")}}
101 -d {{platform.device}}
105 {{invoke_tool("write_fasm")}}
107 -d {{platform.device}}
111 {{invoke_tool("write_bitstream")}}
113 -d {{platform.device}}
124 def add_clock_constraint(self
, clock
, frequency
):
125 super().add_clock_constraint(clock
, frequency
)
126 clock
.attrs
["keep"] = "TRUE"