nmigen/vendor/xilinx_7series.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..lib.cdc import ResetSynchronizer
   5 from ..build import *
   6
   7
   8 __all__ = ["Xilinx7SeriesPlatform"]
   9
  10
  11 class Xilinx7SeriesPlatform(TemplatedPlatform):
  12     """
  13     Required tools:
  14         * ``vivado``
  15
  16     The environment is populated by running the script specified in the environment variable
  17     ``NMIGEN_ENV_Vivado``, if present.
  18
  19     Available overrides:
  20         * ``script_after_read``: inserts commands after ``read_xdc`` in Tcl script.
  21         * ``script_after_synth``: inserts commands after ``synth_design`` in Tcl script.
  22         * ``script_after_place``: inserts commands after ``place_design`` in Tcl script.
  23         * ``script_after_route``: inserts commands after ``route_design`` in Tcl script.
  24         * ``script_before_bitstream``: inserts commands before ``write_bitstream`` in Tcl script.
  25         * ``script_after_bitstream``: inserts commands after ``write_bitstream`` in Tcl script.
  26         * ``add_constraints``: inserts commands in XDC file.
  27         * ``vivado_opts``: adds extra options for ``vivado``.
  28
  29     Build products:
  30         * ``{{name}}.log``: Vivado log.
  31         * ``{{name}}_timing_synth.rpt``: Vivado report.
  32         * ``{{name}}_utilization_hierarchical_synth.rpt``: Vivado report.
  33         * ``{{name}}_utilization_synth.rpt``: Vivado report.
  34         * ``{{name}}_utilization_hierarchical_place.rpt``: Vivado report.
  35         * ``{{name}}_utilization_place.rpt``: Vivado report.
  36         * ``{{name}}_io.rpt``: Vivado report.
  37         * ``{{name}}_control_sets.rpt``: Vivado report.
  38         * ``{{name}}_clock_utilization.rpt``:  Vivado report.
  39         * ``{{name}}_route_status.rpt``: Vivado report.
  40         * ``{{name}}_drc.rpt``: Vivado report.
  41         * ``{{name}}_methodology.rpt``: Vivado report.
  42         * ``{{name}}_timing.rpt``: Vivado report.
  43         * ``{{name}}_power.rpt``: Vivado report.
  44         * ``{{name}}_route.dcp``: Vivado design checkpoint.
  45         * ``{{name}}.bit``: binary bitstream with metadata.
  46         * ``{{name}}.bin``: binary bitstream.
  47     """
  48
  49     toolchain = "Vivado"
  50
  51     device  = abstractproperty()
  52     package = abstractproperty()
  53     speed   = abstractproperty()
  54
  55     required_tools = ["vivado"]
  56     file_templates = {
  57         **TemplatedPlatform.build_script_templates,
  58         "build_{{name}}.sh": r"""
  59             # {{autogenerated}}
  60             set -e{{verbose("x")}}
  61             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
  62             [ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
  63             {{emit_commands("sh")}}
  64         """,
  65         "{{name}}.v": r"""
  66             /* {{autogenerated}} */
  67             {{emit_verilog()}}
  68         """,
  69         "{{name}}.debug.v": r"""
  70             /* {{autogenerated}} */
  71             {{emit_debug_verilog()}}
  72         """,
  73         "{{name}}.tcl": r"""
  74             # {{autogenerated}}
  75             create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
  76             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
  77                 add_files {{file|tcl_escape}}
  78             {% endfor %}
  79             add_files {{name}}.v
  80             read_xdc {{name}}.xdc
  81             {% for file in platform.iter_extra_files(".xdc") -%}
  82                 read_xdc {{file|tcl_escape}}
  83             {% endfor %}
  84             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
  85             synth_design -top {{name}}
  86             foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.false_path == "TRUE"}] {
  87                 set_false_path -to $cell
  88             }
  89             foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.max_delay != ""}] {
  90                 set clock [get_clocks -of_objects \
  91                     [all_fanin -flat -startpoints_only [get_pin $cell/D]]]
  92                 if {[llength $clock] != 0} {
  93                     set_max_delay -datapath_only -from $clock \
  94                         -to [get_cells $cell] [get_property nmigen.vivado.max_delay $cell]
  95                 }
  96             }
  97             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
  98             report_timing_summary -file {{name}}_timing_synth.rpt
  99             report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
 100             report_utilization -file {{name}}_utilization_synth.rpt
 101             opt_design
 102             place_design
 103             {{get_override("script_after_place")|default("# (script_after_place placeholder)")}}
 104             report_utilization -hierarchical -file {{name}}_utilization_hierarchical_place.rpt
 105             report_utilization -file {{name}}_utilization_place.rpt
 106             report_io -file {{name}}_io.rpt
 107             report_control_sets -verbose -file {{name}}_control_sets.rpt
 108             report_clock_utilization -file {{name}}_clock_utilization.rpt
 109             route_design
 110             {{get_override("script_after_route")|default("# (script_after_route placeholder)")}}
 111             phys_opt_design
 112             report_timing_summary -no_header -no_detailed_paths
 113             write_checkpoint -force {{name}}_route.dcp
 114             report_route_status -file {{name}}_route_status.rpt
 115             report_drc -file {{name}}_drc.rpt
 116             report_methodology -file {{name}}_methodology.rpt
 117             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
 118             report_power -file {{name}}_power.rpt
 119             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
 120             write_bitstream -force -bin_file {{name}}.bit
 121             {{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
 122             quit
 123         """,
 124         "{{name}}.xdc": r"""
 125             # {{autogenerated}}
 126             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 127                 set_property LOC {{pin_name}} [get_ports {{port_name|tcl_escape}}]
 128                 {% for attr_name, attr_value in attrs.items() -%}
 129                     set_property {{attr_name}} {{attr_value|tcl_escape}} [get_ports {{port_name|tcl_escape}}]
 130                 {% endfor %}
 131             {% endfor %}
 132             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 133                 {% if port_signal is not none -%}
 134                     create_clock -name {{port_signal.name|ascii_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 135                 {% else -%}
 136                     create_clock -name {{net_signal.name|ascii_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 137                 {% endif %}
 138             {% endfor %}
 139             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 140         """
 141     }
 142     command_templates = [
 143         r"""
 144         {{invoke_tool("vivado")}}
 145             {{verbose("-verbose")}}
 146             {{get_override("vivado_opts")|options}}
 147             -mode batch
 148             -log {{name}}.log
 149             -source {{name}}.tcl
 150         """
 151     ]
 152
 153     def create_missing_domain(self, name):
 154         # Xilinx devices have a global write enable (GWE) signal that asserted during configuraiton
 155         # and deasserted once it ends. Because it is an asynchronous signal (GWE is driven by logic
 156         # syncronous to configuration clock, which is not used by most designs), even though it is
 157         # a low-skew global network, its deassertion may violate a setup/hold constraint with
 158         # relation to a user clock. The recommended solution is to use a BUFGCE driven by the EOS
 159         # signal. For details, see:
 160         #   * https://www.xilinx.com/support/answers/44174.html
 161         #   * https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
 162         if name == "sync" and self.default_clk is not None:
 163             clk_i = self.request(self.default_clk).i
 164             if self.default_rst is not None:
 165                 rst_i = self.request(self.default_rst).i
 166
 167             m = Module()
 168             ready = Signal()
 169             m.submodules += Instance("STARTUPE2", o_EOS=ready)
 170             m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
 171             # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth
 172             # mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter)
 173             # breaks Vivado 2017.4.
 174             m.submodules += Instance("BUFGCTRL",
 175                 i_I0=clk_i,   i_S0=C(1, 1), i_CE0=ready,   i_IGNORE0=C(0, 1),
 176                 i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1),
 177                 o_O=ClockSignal("sync")
 178             )
 179             if self.default_rst is not None:
 180                 m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
 181             return m
 182
 183     def add_clock_constraint(self, clock, frequency):
 184         super().add_clock_constraint(clock, frequency)
 185         clock.attrs["keep"] = "TRUE"
 186
 187     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 188         def get_dff(clk, d, q):
 189             # SDR I/O is performed by packing a flip-flop into the pad IOB.
 190             for bit in range(len(q)):
 191                 m.submodules += Instance("FDCE",
 192                     a_IOB="TRUE",
 193                     i_C=clk,
 194                     i_CE=Const(1),
 195                     i_CLR=Const(0),
 196                     i_D=d[bit],
 197                     o_Q=q[bit]
 198                 )
 199
 200         def get_iddr(clk, d, q1, q2):
 201             for bit in range(len(q1)):
 202                 m.submodules += Instance("IDDR",
 203                     p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
 204                     p_SRTYPE="ASYNC",
 205                     p_INIT_Q1=0, p_INIT_Q2=0,
 206                     i_C=clk,
 207                     i_CE=Const(1),
 208                     i_S=Const(0), i_R=Const(0),
 209                     i_D=d[bit],
 210                     o_Q1=q1[bit], o_Q2=q2[bit]
 211                 )
 212
 213         def get_oddr(clk, d1, d2, q):
 214             for bit in range(len(q)):
 215                 m.submodules += Instance("ODDR",
 216                     p_DDR_CLK_EDGE="SAME_EDGE",
 217                     p_SRTYPE="ASYNC",
 218                     p_INIT=0,
 219                     i_C=clk,
 220                     i_CE=Const(1),
 221                     i_S=Const(0), i_R=Const(0),
 222                     i_D1=d1[bit], i_D2=d2[bit],
 223                     o_Q=q[bit]
 224                 )
 225
 226         def get_ineg(y, invert):
 227             if invert:
 228                 a = Signal.like(y, name_suffix="_n")
 229                 m.d.comb += y.eq(~a)
 230                 return a
 231             else:
 232                 return y
 233
 234         def get_oneg(a, invert):
 235             if invert:
 236                 y = Signal.like(a, name_suffix="_n")
 237                 m.d.comb += y.eq(~a)
 238                 return y
 239             else:
 240                 return a
 241
 242         if "i" in pin.dir:
 243             if pin.xdr < 2:
 244                 pin_i  = get_ineg(pin.i,  i_invert)
 245             elif pin.xdr == 2:
 246                 pin_i0 = get_ineg(pin.i0, i_invert)
 247                 pin_i1 = get_ineg(pin.i1, i_invert)
 248         if "o" in pin.dir:
 249             if pin.xdr < 2:
 250                 pin_o  = get_oneg(pin.o,  o_invert)
 251             elif pin.xdr == 2:
 252                 pin_o0 = get_oneg(pin.o0, o_invert)
 253                 pin_o1 = get_oneg(pin.o1, o_invert)
 254
 255         i = o = t = None
 256         if "i" in pin.dir:
 257             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 258         if "o" in pin.dir:
 259             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 260         if pin.dir in ("oe", "io"):
 261             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 262
 263         if pin.xdr == 0:
 264             if "i" in pin.dir:
 265                 i = pin_i
 266             if "o" in pin.dir:
 267                 o = pin_o
 268             if pin.dir in ("oe", "io"):
 269                 t = ~pin.oe
 270         elif pin.xdr == 1:
 271             if "i" in pin.dir:
 272                 get_dff(pin.i_clk, i, pin_i)
 273             if "o" in pin.dir:
 274                 get_dff(pin.o_clk, pin_o, o)
 275             if pin.dir in ("oe", "io"):
 276                 get_dff(pin.o_clk, ~pin.oe, t)
 277         elif pin.xdr == 2:
 278             if "i" in pin.dir:
 279                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 280             if "o" in pin.dir:
 281                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 282             if pin.dir in ("oe", "io"):
 283                 get_dff(pin.o_clk, ~pin.oe, t)
 284         else:
 285             assert False
 286
 287         return (i, o, t)
 288
 289     def get_input(self, pin, port, attrs, invert):
 290         self._check_feature("single-ended input", pin, attrs,
 291                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 292         m = Module()
 293         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 294         for bit in range(pin.width):
 295             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
 296                 i_I=port.io[bit],
 297                 o_O=i[bit]
 298             )
 299         return m
 300
 301     def get_output(self, pin, port, attrs, invert):
 302         self._check_feature("single-ended output", pin, attrs,
 303                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 304         m = Module()
 305         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 306         for bit in range(pin.width):
 307             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
 308                 i_I=o[bit],
 309                 o_O=port.io[bit]
 310             )
 311         return m
 312
 313     def get_tristate(self, pin, port, attrs, invert):
 314         self._check_feature("single-ended tristate", pin, attrs,
 315                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 316         m = Module()
 317         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 318         for bit in range(pin.width):
 319             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
 320                 i_T=t,
 321                 i_I=o[bit],
 322                 o_O=port.io[bit]
 323             )
 324         return m
 325
 326     def get_input_output(self, pin, port, attrs, invert):
 327         self._check_feature("single-ended input/output", pin, attrs,
 328                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 329         m = Module()
 330         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 331         for bit in range(pin.width):
 332             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
 333                 i_T=t,
 334                 i_I=o[bit],
 335                 o_O=i[bit],
 336                 io_IO=port.io[bit]
 337             )
 338         return m
 339
 340     def get_diff_input(self, pin, port, attrs, invert):
 341         self._check_feature("differential input", pin, attrs,
 342                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 343         m = Module()
 344         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 345         for bit in range(pin.width):
 346             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
 347                 i_I=port.p[bit], i_IB=port.n[bit],
 348                 o_O=i[bit]
 349             )
 350         return m
 351
 352     def get_diff_output(self, pin, port, attrs, invert):
 353         self._check_feature("differential output", pin, attrs,
 354                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 355         m = Module()
 356         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 357         for bit in range(pin.width):
 358             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
 359                 i_I=o[bit],
 360                 o_O=port.p[bit], o_OB=port.n[bit]
 361             )
 362         return m
 363
 364     def get_diff_tristate(self, pin, port, attrs, invert):
 365         self._check_feature("differential tristate", pin, attrs,
 366                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 367         m = Module()
 368         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 369         for bit in range(pin.width):
 370             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
 371                 i_T=t,
 372                 i_I=o[bit],
 373                 o_O=port.p[bit], o_OB=port.n[bit]
 374             )
 375         return m
 376
 377     def get_diff_input_output(self, pin, port, attrs, invert):
 378         self._check_feature("differential input/output", pin, attrs,
 379                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 380         m = Module()
 381         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 382         for bit in range(pin.width):
 383             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
 384                 i_T=t,
 385                 i_I=o[bit],
 386                 o_O=i[bit],
 387                 io_IO=port.p[bit], io_IOB=port.n[bit]
 388             )
 389         return m
 390
 391     # The synchronizer implementations below apply two separate but related timing constraints.
 392     #
 393     # First, the ASYNC_REG attribute prevents inference of shift registers from synchronizer FFs,
 394     # and constraints the FFs to be placed as close as possible, ideally in one CLB. This attribute
 395     # only affects the synchronizer FFs themselves.
 396     #
 397     # Second, the nmigen.vivado.false_path or nmigen.vivado.max_delay attribute affects the path
 398     # into the synchronizer. If maximum input delay is specified, a datapath-only maximum delay
 399     # constraint is applied, limiting routing delay (and therefore skew) at the synchronizer input.
 400     # Otherwise, a false path constraint is used to omit the input path from the timing analysis.
 401
 402     def get_ff_sync(self, ff_sync):
 403         m = Module()
 404         flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
 405                         reset=ff_sync._reset, reset_less=ff_sync._reset_less,
 406                         attrs={"ASYNC_REG": "TRUE"})
 407                  for index in range(ff_sync._stages)]
 408         if ff_sync._max_input_delay is None:
 409             flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
 410         else:
 411             flops[0].attrs["nmigen.vivado.max_delay"] = str(ff_sync._max_input_delay * 1e9)
 412         for i, o in zip((ff_sync.i, *flops), flops):
 413             m.d[ff_sync._o_domain] += o.eq(i)
 414         m.d.comb += ff_sync.o.eq(flops[-1])
 415         return m
 416
 417     def get_async_ff_sync(self, async_ff_sync):
 418         m = Module()
 419         m.domains += ClockDomain("async_ff", async_reset=True, local=True)
 420         flops = [Signal(1, name="stage{}".format(index), reset=1,
 421                         attrs={"ASYNC_REG": "TRUE"})
 422                  for index in range(async_ff_sync._stages)]
 423         if async_ff_sync._max_input_delay is None:
 424             flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
 425         else:
 426             flops[0].attrs["nmigen.vivado.max_delay"] = str(async_ff_sync._max_input_delay * 1e9)
 427         for i, o in zip((0, *flops), flops):
 428             m.d.async_ff += o.eq(i)
 429
 430         if async_ff_sync._edge == "pos":
 431             m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i)
 432         else:
 433             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 434
 435         m.d.comb += [
 436             ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
 437             async_ff_sync.o.eq(flops[-1])
 438         ]
 439
 440         return m