nmigen/vendor/xilinx_7series.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..lib.cdc import ResetSynchronizer
   5 from ..build import *
   6
   7
   8 __all__ = ["Xilinx7SeriesPlatform"]
   9
  10
  11 class Xilinx7SeriesPlatform(TemplatedPlatform):
  12     """
  13     Required tools:
  14         * ``vivado``
  15
  16     The environment is populated by running the script specified in the environment variable
  17     ``NMIGEN_ENV_Vivado``, if present.
  18
  19     Available overrides:
  20         * ``script_after_read``: inserts commands after ``read_xdc`` in Tcl script.
  21         * ``script_after_synth``: inserts commands after ``synth_design`` in Tcl script.
  22         * ``script_after_place``: inserts commands after ``place_design`` in Tcl script.
  23         * ``script_after_route``: inserts commands after ``route_design`` in Tcl script.
  24         * ``script_before_bitstream``: inserts commands before ``write_bitstream`` in Tcl script.
  25         * ``script_after_bitstream``: inserts commands after ``write_bitstream`` in Tcl script.
  26         * ``add_constraints``: inserts commands in XDC file.
  27         * ``vivado_opts``: adds extra options for ``vivado``.
  28
  29     Build products:
  30         * ``{{name}}.log``: Vivado log.
  31         * ``{{name}}_timing_synth.rpt``: Vivado report.
  32         * ``{{name}}_utilization_hierarchical_synth.rpt``: Vivado report.
  33         * ``{{name}}_utilization_synth.rpt``: Vivado report.
  34         * ``{{name}}_utilization_hierarchical_place.rpt``: Vivado report.
  35         * ``{{name}}_utilization_place.rpt``: Vivado report.
  36         * ``{{name}}_io.rpt``: Vivado report.
  37         * ``{{name}}_control_sets.rpt``: Vivado report.
  38         * ``{{name}}_clock_utilization.rpt``:  Vivado report.
  39         * ``{{name}}_route_status.rpt``: Vivado report.
  40         * ``{{name}}_drc.rpt``: Vivado report.
  41         * ``{{name}}_methodology.rpt``: Vivado report.
  42         * ``{{name}}_timing.rpt``: Vivado report.
  43         * ``{{name}}_power.rpt``: Vivado report.
  44         * ``{{name}}_route.dcp``: Vivado design checkpoint.
  45         * ``{{name}}.bit``: binary bitstream with metadata.
  46         * ``{{name}}.bin``: binary bitstream.
  47     """
  48
  49     toolchain = "Vivado"
  50
  51     device  = abstractproperty()
  52     package = abstractproperty()
  53     speed   = abstractproperty()
  54
  55     @property
  56     def _part(self):
  57         return "{}{}-{}".format(self.device, self.package, self.speed)
  58
  59     required_tools = ["vivado"]
  60     file_templates = {
  61         **TemplatedPlatform.build_script_templates,
  62         "build_{{name}}.sh": r"""
  63             # {{autogenerated}}
  64             set -e{{verbose("x")}}
  65             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
  66             [ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
  67             {{emit_commands("sh")}}
  68         """,
  69         "{{name}}.v": r"""
  70             /* {{autogenerated}} */
  71             {{emit_verilog()}}
  72         """,
  73         "{{name}}.debug.v": r"""
  74             /* {{autogenerated}} */
  75             {{emit_debug_verilog()}}
  76         """,
  77         "{{name}}.tcl": r"""
  78             # {{autogenerated}}
  79             create_project -force -name {{name}} -part {{platform._part}}
  80             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
  81                 add_files {{file|tcl_escape}}
  82             {% endfor %}
  83             add_files {{name}}.v
  84             read_xdc {{name}}.xdc
  85             {% for file in platform.iter_extra_files(".xdc") -%}
  86                 read_xdc {{file|tcl_escape}}
  87             {% endfor %}
  88             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
  89             synth_design -top {{name}}
  90             foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.false_path == "TRUE"}] {
  91                 set_false_path -to $cell
  92             }
  93             foreach cell [get_cells -quiet -hier -filter {nmigen.vivado.max_delay != ""}] {
  94                 set clock [get_clocks -of_objects \
  95                     [all_fanin -flat -startpoints_only [get_pin $cell/D]]]
  96                 if {[llength $clock] != 0} {
  97                     set_max_delay -datapath_only -from $clock \
  98                         -to [get_cells $cell] [get_property nmigen.vivado.max_delay $cell]
  99                 }
 100             }
 101             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
 102             report_timing_summary -file {{name}}_timing_synth.rpt
 103             report_utilization -hierarchical -file {{name}}_utilization_hierachical_synth.rpt
 104             report_utilization -file {{name}}_utilization_synth.rpt
 105             opt_design
 106             place_design
 107             {{get_override("script_after_place")|default("# (script_after_place placeholder)")}}
 108             report_utilization -hierarchical -file {{name}}_utilization_hierarchical_place.rpt
 109             report_utilization -file {{name}}_utilization_place.rpt
 110             report_io -file {{name}}_io.rpt
 111             report_control_sets -verbose -file {{name}}_control_sets.rpt
 112             report_clock_utilization -file {{name}}_clock_utilization.rpt
 113             route_design
 114             {{get_override("script_after_route")|default("# (script_after_route placeholder)")}}
 115             phys_opt_design
 116             report_timing_summary -no_header -no_detailed_paths
 117             write_checkpoint -force {{name}}_route.dcp
 118             report_route_status -file {{name}}_route_status.rpt
 119             report_drc -file {{name}}_drc.rpt
 120             report_methodology -file {{name}}_methodology.rpt
 121             report_timing_summary -datasheet -max_paths 10 -file {{name}}_timing.rpt
 122             report_power -file {{name}}_power.rpt
 123             {{get_override("script_before_bitstream")|default("# (script_before_bitstream placeholder)")}}
 124             write_bitstream -force -bin_file {{name}}.bit
 125             {{get_override("script_after_bitstream")|default("# (script_after_bitstream placeholder)")}}
 126             quit
 127         """,
 128         "{{name}}.xdc": r"""
 129             # {{autogenerated}}
 130             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 131                 set_property LOC {{pin_name}} [get_ports {{port_name|tcl_escape}}]
 132                 {% for attr_name, attr_value in attrs.items() -%}
 133                     set_property {{attr_name}} {{attr_value|tcl_escape}} [get_ports {{port_name|tcl_escape}}]
 134                 {% endfor %}
 135             {% endfor %}
 136             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 137                 {% if port_signal is not none -%}
 138                     create_clock -name {{port_signal.name|ascii_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 139                 {% else -%}
 140                     create_clock -name {{net_signal.name|ascii_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 141                 {% endif %}
 142             {% endfor %}
 143             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 144         """
 145     }
 146     command_templates = [
 147         r"""
 148         {{invoke_tool("vivado")}}
 149             {{verbose("-verbose")}}
 150             {{get_override("vivado_opts")|options}}
 151             -mode batch
 152             -log {{name}}.log
 153             -source {{name}}.tcl
 154         """
 155     ]
 156
 157     def create_missing_domain(self, name):
 158         # Xilinx devices have a global write enable (GWE) signal that asserted during configuraiton
 159         # and deasserted once it ends. Because it is an asynchronous signal (GWE is driven by logic
 160         # syncronous to configuration clock, which is not used by most designs), even though it is
 161         # a low-skew global network, its deassertion may violate a setup/hold constraint with
 162         # relation to a user clock. The recommended solution is to use a BUFGCE driven by the EOS
 163         # signal. For details, see:
 164         #   * https://www.xilinx.com/support/answers/44174.html
 165         #   * https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
 166         if name == "sync" and self.default_clk is not None:
 167             clk_i = self.request(self.default_clk).i
 168             if self.default_rst is not None:
 169                 rst_i = self.request(self.default_rst).i
 170
 171             m = Module()
 172             ready = Signal()
 173             m.submodules += Instance("STARTUPE2", o_EOS=ready)
 174             m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
 175             # Actually use BUFGCTRL configured as BUFGCE, since using BUFGCE causes sim/synth
 176             # mismatches with Vivado 2019.2, and the suggested workaround (SIM_DEVICE parameter)
 177             # breaks Vivado 2017.4.
 178             m.submodules += Instance("BUFGCTRL",
 179                 i_I0=clk_i,   i_S0=C(1, 1), i_CE0=ready,   i_IGNORE0=C(0, 1),
 180                 i_I1=C(1, 1), i_S1=C(0, 1), i_CE1=C(0, 1), i_IGNORE1=C(1, 1),
 181                 o_O=ClockSignal("sync")
 182             )
 183             if self.default_rst is not None:
 184                 m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
 185             return m
 186
 187     def add_clock_constraint(self, clock, frequency):
 188         super().add_clock_constraint(clock, frequency)
 189         clock.attrs["keep"] = "TRUE"
 190
 191     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 192         def get_dff(clk, d, q):
 193             # SDR I/O is performed by packing a flip-flop into the pad IOB.
 194             for bit in range(len(q)):
 195                 m.submodules += Instance("FDCE",
 196                     a_IOB="TRUE",
 197                     i_C=clk,
 198                     i_CE=Const(1),
 199                     i_CLR=Const(0),
 200                     i_D=d[bit],
 201                     o_Q=q[bit]
 202                 )
 203
 204         def get_iddr(clk, d, q1, q2):
 205             for bit in range(len(q1)):
 206                 m.submodules += Instance("IDDR",
 207                     p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
 208                     p_SRTYPE="ASYNC",
 209                     p_INIT_Q1=0, p_INIT_Q2=0,
 210                     i_C=clk,
 211                     i_CE=Const(1),
 212                     i_S=Const(0), i_R=Const(0),
 213                     i_D=d[bit],
 214                     o_Q1=q1[bit], o_Q2=q2[bit]
 215                 )
 216
 217         def get_oddr(clk, d1, d2, q):
 218             for bit in range(len(q)):
 219                 m.submodules += Instance("ODDR",
 220                     p_DDR_CLK_EDGE="SAME_EDGE",
 221                     p_SRTYPE="ASYNC",
 222                     p_INIT=0,
 223                     i_C=clk,
 224                     i_CE=Const(1),
 225                     i_S=Const(0), i_R=Const(0),
 226                     i_D1=d1[bit], i_D2=d2[bit],
 227                     o_Q=q[bit]
 228                 )
 229
 230         def get_ineg(y, invert):
 231             if invert:
 232                 a = Signal.like(y, name_suffix="_n")
 233                 m.d.comb += y.eq(~a)
 234                 return a
 235             else:
 236                 return y
 237
 238         def get_oneg(a, invert):
 239             if invert:
 240                 y = Signal.like(a, name_suffix="_n")
 241                 m.d.comb += y.eq(~a)
 242                 return y
 243             else:
 244                 return a
 245
 246         if "i" in pin.dir:
 247             if pin.xdr < 2:
 248                 pin_i  = get_ineg(pin.i,  i_invert)
 249             elif pin.xdr == 2:
 250                 pin_i0 = get_ineg(pin.i0, i_invert)
 251                 pin_i1 = get_ineg(pin.i1, i_invert)
 252         if "o" in pin.dir:
 253             if pin.xdr < 2:
 254                 pin_o  = get_oneg(pin.o,  o_invert)
 255             elif pin.xdr == 2:
 256                 pin_o0 = get_oneg(pin.o0, o_invert)
 257                 pin_o1 = get_oneg(pin.o1, o_invert)
 258
 259         i = o = t = None
 260         if "i" in pin.dir:
 261             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 262         if "o" in pin.dir:
 263             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 264         if pin.dir in ("oe", "io"):
 265             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 266
 267         if pin.xdr == 0:
 268             if "i" in pin.dir:
 269                 i = pin_i
 270             if "o" in pin.dir:
 271                 o = pin_o
 272             if pin.dir in ("oe", "io"):
 273                 t = ~pin.oe
 274         elif pin.xdr == 1:
 275             if "i" in pin.dir:
 276                 get_dff(pin.i_clk, i, pin_i)
 277             if "o" in pin.dir:
 278                 get_dff(pin.o_clk, pin_o, o)
 279             if pin.dir in ("oe", "io"):
 280                 get_dff(pin.o_clk, ~pin.oe, t)
 281         elif pin.xdr == 2:
 282             if "i" in pin.dir:
 283                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 284             if "o" in pin.dir:
 285                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 286             if pin.dir in ("oe", "io"):
 287                 get_dff(pin.o_clk, ~pin.oe, t)
 288         else:
 289             assert False
 290
 291         return (i, o, t)
 292
 293     def get_input(self, pin, port, attrs, invert):
 294         self._check_feature("single-ended input", pin, attrs,
 295                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 296         m = Module()
 297         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 298         for bit in range(pin.width):
 299             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
 300                 i_I=port.io[bit],
 301                 o_O=i[bit]
 302             )
 303         return m
 304
 305     def get_output(self, pin, port, attrs, invert):
 306         self._check_feature("single-ended output", pin, attrs,
 307                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 308         m = Module()
 309         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 310         for bit in range(pin.width):
 311             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
 312                 i_I=o[bit],
 313                 o_O=port.io[bit]
 314             )
 315         return m
 316
 317     def get_tristate(self, pin, port, attrs, invert):
 318         self._check_feature("single-ended tristate", pin, attrs,
 319                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 320         m = Module()
 321         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 322         for bit in range(pin.width):
 323             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
 324                 i_T=t,
 325                 i_I=o[bit],
 326                 o_O=port.io[bit]
 327             )
 328         return m
 329
 330     def get_input_output(self, pin, port, attrs, invert):
 331         self._check_feature("single-ended input/output", pin, attrs,
 332                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 333         m = Module()
 334         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 335         for bit in range(pin.width):
 336             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
 337                 i_T=t,
 338                 i_I=o[bit],
 339                 o_O=i[bit],
 340                 io_IO=port.io[bit]
 341             )
 342         return m
 343
 344     def get_diff_input(self, pin, port, attrs, invert):
 345         self._check_feature("differential input", pin, attrs,
 346                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 347         m = Module()
 348         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 349         for bit in range(pin.width):
 350             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
 351                 i_I=port.p[bit], i_IB=port.n[bit],
 352                 o_O=i[bit]
 353             )
 354         return m
 355
 356     def get_diff_output(self, pin, port, attrs, invert):
 357         self._check_feature("differential output", pin, attrs,
 358                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 359         m = Module()
 360         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 361         for bit in range(pin.width):
 362             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
 363                 i_I=o[bit],
 364                 o_O=port.p[bit], o_OB=port.n[bit]
 365             )
 366         return m
 367
 368     def get_diff_tristate(self, pin, port, attrs, invert):
 369         self._check_feature("differential tristate", pin, attrs,
 370                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 371         m = Module()
 372         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 373         for bit in range(pin.width):
 374             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
 375                 i_T=t,
 376                 i_I=o[bit],
 377                 o_O=port.p[bit], o_OB=port.n[bit]
 378             )
 379         return m
 380
 381     def get_diff_input_output(self, pin, port, attrs, invert):
 382         self._check_feature("differential input/output", pin, attrs,
 383                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 384         m = Module()
 385         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 386         for bit in range(pin.width):
 387             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
 388                 i_T=t,
 389                 i_I=o[bit],
 390                 o_O=i[bit],
 391                 io_IO=port.p[bit], io_IOB=port.n[bit]
 392             )
 393         return m
 394
 395     # The synchronizer implementations below apply two separate but related timing constraints.
 396     #
 397     # First, the ASYNC_REG attribute prevents inference of shift registers from synchronizer FFs,
 398     # and constraints the FFs to be placed as close as possible, ideally in one CLB. This attribute
 399     # only affects the synchronizer FFs themselves.
 400     #
 401     # Second, the nmigen.vivado.false_path or nmigen.vivado.max_delay attribute affects the path
 402     # into the synchronizer. If maximum input delay is specified, a datapath-only maximum delay
 403     # constraint is applied, limiting routing delay (and therefore skew) at the synchronizer input.
 404     # Otherwise, a false path constraint is used to omit the input path from the timing analysis.
 405
 406     def get_ff_sync(self, ff_sync):
 407         m = Module()
 408         flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
 409                         reset=ff_sync._reset, reset_less=ff_sync._reset_less,
 410                         attrs={"ASYNC_REG": "TRUE"})
 411                  for index in range(ff_sync._stages)]
 412         if ff_sync._max_input_delay is None:
 413             flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
 414         else:
 415             flops[0].attrs["nmigen.vivado.max_delay"] = str(ff_sync._max_input_delay * 1e9)
 416         for i, o in zip((ff_sync.i, *flops), flops):
 417             m.d[ff_sync._o_domain] += o.eq(i)
 418         m.d.comb += ff_sync.o.eq(flops[-1])
 419         return m
 420
 421     def get_async_ff_sync(self, async_ff_sync):
 422         m = Module()
 423         m.domains += ClockDomain("async_ff", async_reset=True, local=True)
 424         flops = [Signal(1, name="stage{}".format(index), reset=1,
 425                         attrs={"ASYNC_REG": "TRUE"})
 426                  for index in range(async_ff_sync._stages)]
 427         if async_ff_sync._max_input_delay is None:
 428             flops[0].attrs["nmigen.vivado.false_path"] = "TRUE"
 429         else:
 430             flops[0].attrs["nmigen.vivado.max_delay"] = str(async_ff_sync._max_input_delay * 1e9)
 431         for i, o in zip((0, *flops), flops):
 432             m.d.async_ff += o.eq(i)
 433
 434         if async_ff_sync._edge == "pos":
 435             m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i)
 436         else:
 437             m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i)
 438
 439         m.d.comb += [
 440             ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)),
 441             async_ff_sync.o.eq(flops[-1])
 442         ]
 443
 444         return m