4 from nmigen
.build
import *
5 from nmigen
.vendor
.xilinx_7series
import *
9 __all__
= ["ArtyA7Platform"]
12 class ArtyA7Platform(Xilinx7SeriesPlatform
):
16 default_clk
= "clk100"
18 Resource("clk100", 0, Pins("E3", dir="i"),
19 Clock(100e6
), Attrs(IOSTANDARD
="LVCMOS33")),
21 *LEDResources(pins
="H5 J5 T9 T10", attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
23 RGBLEDResource(0, r
="G6", g
="F6", b
="E1", attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
24 RGBLEDResource(1, r
="G3", g
="J4", b
="G4", attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
25 RGBLEDResource(2, r
="J3", g
="J2", b
="H4", attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
26 RGBLEDResource(3, r
="K1", g
="H6", b
="K2", attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
28 *ButtonResources(pins
="D9 C9 B9 B8 ", attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
29 *SwitchResources(pins
="A8 C11 C10 A10", attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
33 attrs
=Attrs(IOSTANDARD
="LVCMOS33")
36 Resource("cpu_reset", 0, Pins("C2", dir="o"), Attrs(IOSTANDARD
="LVCMOS33")),
39 cs
="C1", clk
="F1", mosi
="H1", miso
="G1",
40 attrs
=Attrs(IOSTANDARD
="LVCMOS33")
44 Subsignal("scl", Pins("L18", dir="io")),
45 Subsignal("sda", Pins("M18", dir="io")),
46 Subsignal("scl_pullup", Pins("A14", dir="o")),
47 Subsignal("sda_pullup", Pins("A13", dir="o")),
48 Attrs(IOSTANDARD
="LVCMOS33")
52 cs
="L13", clk
="L16", mosi
="K17", miso
="K18", wp
="L14", hold
="M14",
53 attrs
=Attrs(IOSTANDARD
="LVCMOS33")
57 Subsignal("rst", PinsN("K6", dir="o")),
58 Subsignal("clk", DiffPairs("U9", "V9", dir="o"), Attrs(IOSTANDARD
="DIFF_SSTL135")),
59 Subsignal("clk_en", Pins("N5", dir="o")),
60 Subsignal("cs", PinsN("U8", dir="o")),
61 Subsignal("we", PinsN("P5", dir="o")),
62 Subsignal("ras", PinsN("P3", dir="o")),
63 Subsignal("cas", PinsN("M4", dir="o")),
64 Subsignal("a", Pins("R2 M6 N4 T1 N6 R7 V6 U7 R8 V7 R6 U6 T6 T8", dir="o")),
65 Subsignal("ba", Pins("R1 P4 P2", dir="o")),
66 Subsignal("dqs", DiffPairs("N2 U2", "N1 V2", dir="io"),
67 Attrs(IOSTANDARD
="DIFF_SSTL135")),
68 Subsignal("dq", Pins("K5 L3 K3 L6 M3 M1 L4 M2 V4 T5 U4 V5 V1 T3 U3 R3", dir="io"),
69 Attrs(IN_TERM
="UNTUNED_SPLIT_40")),
70 Subsignal("dm", Pins("L1 U1", dir="o")),
71 Subsignal("odt", Pins("R5", dir="o")),
72 Attrs(IOSTANDARD
="SSTL135", SLEW
="FAST"),
75 Resource("eth_clk25", 0, Pins("G18", dir="o"),
76 Clock(25e6
), Attrs(IOSTANDARD
="LVCMOS33")),
77 Resource("eth_clk50", 0, Pins("G18", dir="o"),
78 Clock(50e6
), Attrs(IOSTANDARD
="LVCMOS33")),
79 Resource("eth_mii", 0,
80 Subsignal("rst", PinsN("C16", dir="o")),
81 Subsignal("mdio", Pins("K13", dir="io")),
82 Subsignal("mdc", Pins("F16", dir="o")),
83 Subsignal("tx_clk", Pins("H16", dir="i")),
84 Subsignal("tx_en", Pins("H15", dir="o")),
85 Subsignal("tx_data", Pins("H14 J14 J13 H17", dir="o")),
86 Subsignal("rx_clk", Pins("F15", dir="i")),
87 Subsignal("rx_dv", Pins("G16", dir="i"), Attrs(PULLDOWN
="TRUE")), # strap to select MII
88 Subsignal("rx_er", Pins("C17", dir="i")),
89 Subsignal("rx_data", Pins("D18 E17 E18 G17", dir="i")),
90 Subsignal("col", Pins("D17", dir="i")),
91 Subsignal("crs", Pins("G14", dir="i")),
92 Attrs(IOSTANDARD
="LVCMOS33")
94 Resource("eth_rmii", 0,
95 Subsignal("rst", PinsN("C16", dir="o")),
96 Subsignal("mdio", Pins("K13", dir="io")),
97 Subsignal("mdc", Pins("F16", dir="o")),
98 Subsignal("tx_en", Pins("H15", dir="o")),
99 Subsignal("tx_data", Pins("H14 J14", dir="o")),
100 Subsignal("rx_crs_dv", Pins("G14", dir="i")),
101 Subsignal("rx_dv", Pins("G16", dir="i"), Attrs(PULLUP
="TRUE")), # strap to select RMII
102 Subsignal("rx_er", Pins("C17", dir="i")),
103 Subsignal("rx_data", Pins("D18 E17", dir="i")),
104 Attrs(IOSTANDARD
="LVCMOS33")
108 Connector("pmod", 0, "G13 B11 A11 D12 - - D13 B18 A18 K16 - -"), # JA
109 Connector("pmod", 1, "E15 E16 D15 C15 - - J17 J18 K15 J15 - -"), # JB
110 Connector("pmod", 2, "U12 V12 V10 V11 - - U14 V14 T13 U13 - -"), # JC
111 Connector("pmod", 3, " D4 D3 F4 F3 - - E2 D2 H2 G2 - -"), # JD
113 Connector("ck_io", 0, {
114 # Outer Digital Header
130 # Inner Digital Header
148 # Outer Analog Header as Digital IO
156 # Inner Analog Header as Digital IO
164 Connector("xadc", 0, {
165 # Outer Analog Header
179 # Inner Analog Header
199 def toolchain_prepare(self
, fragment
, name
, **kwargs
):
201 "script_before_bitstream":
202 "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
203 "script_after_bitstream":
204 "write_cfgmem -force -format bin -interface spix4 -size 16 "
205 "-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name
=name
),
207 "set_property INTERNAL_VREF 0.675 [get_iobanks 34]"
209 return super().toolchain_prepare(fragment
, name
, **overrides
, **kwargs
)
211 def toolchain_program(self
, products
, name
):
212 xc3sprog
= os
.environ
.get("XC3SPROG", "xc3sprog")
213 with products
.extract("{}.bit".format(name
)) as bitstream_filename
:
214 subprocess
.run([xc3sprog
, "-c", "nexys4", bitstream_filename
], check
=True)
217 if __name__
== "__main__":
218 from ._blinky
import Blinky
219 ArtyA7Platform().build(Blinky(), do_program
=True)