artyz7: fix attribute name.
[nmigen-boards.git] / nmigen_boards / arty_z7.py
1 import os
2 import subprocess
3
4 from nmigen.build import *
5 from nmigen.vendor.xilinx_7series import *
6 from .resources import *
7
8
9 __all__ = ["ArtyZ720Platform"]
10
11
12 class ArtyZ720Platform(Xilinx7SeriesPlatform):
13 device = "xc7z020"
14 package = "clg400"
15 speed = "1"
16 default_clk = "clk125"
17 resources = [
18 Resource("clk125", 0,
19 Pins("H16", dir="i"), Clock(125e6), Attrs(IOSTANDARD="LVCMOS33")),
20
21 *SwitchResources(
22 pins="M20 M19",
23 attrs=Attrs(IOSTANDARD="LVCMOS33")),
24
25 RGBLEDResource(0,
26 r="N15", g="G17", b="L15", # LD4
27 attrs=Attrs(IOSTANDARD="LVCMOS33")),
28 RGBLEDResource(1, # LD5
29 r="M15", g="L14", b="G14",
30 attrs=Attrs(IOSTANDARD="LVCMOS33")),
31
32 *LEDResources(
33 pins="R14 P14 N16 M14",
34 attrs=Attrs(IOSTANDARD="LVCMOS33")),
35
36 *ButtonResources(
37 pins="D19 D20 L20 L19",
38 attrs=Attrs(IOSTANDARD="LVCMOS33")),
39
40 Resource("audio", 0,
41 Subsignal("pwm", Pins("R18", dir="o")),
42 Subsignal("sd", PinsN("T17", dir="o")),
43 Attrs(IOSTANDARD="LVCMOS33")),
44
45 Resource("crypto_sda", 0, # ATSHA204A
46 Pins("J15", dir="io"),
47 Attrs(IOSTANDARD="LVCMOS33")),
48
49 Resource("hdmi_rx", 0, # J10
50 Subsignal("cec", Pins("H17", dir="io")),
51 Subsignal("clk", DiffPairs("N18", "P19", dir="i"),
52 Attrs(IOSTANDARD="TMDS_33")),
53 Subsignal("d", DiffPairs("V20 T20 N20", "W20 U20 P20", dir="i"),
54 Attrs(IOSTANDARD="TMDS_33")),
55 Subsignal("hpd", Pins("T19", dir="o")),
56 Subsignal("scl", Pins("U14", dir="io")),
57 Subsignal("sda", Pins("U15", dir="io")),
58 Attrs(IOSTANDARD="LVCMOS33")),
59
60 Resource("hdmi_tx", 0, # J11
61 Subsignal("cec", Pins("G15", dir="io")),
62 Subsignal("clk", DiffPairs("L16", "L17", dir="o"),
63 Attrs(IOSTANDARD="TMDS_33")),
64 Subsignal("d", DiffPairs("K17 K19 J18", "K18 J19 H18", dir="o"),
65 Attrs(IOSTANDARD="TMDS_33")),
66 Subsignal("hpd", PinsN("R19", dir="i")),
67 Subsignal("scl", Pins("M17", dir="io")),
68 Subsignal("sda", Pins("M18", dir="io")),
69 Attrs(IOSTANDARD="LVCMOS33"))
70 ]
71 connectors = [
72 Connector("pmod", 0, "Y18 Y19 Y16 Y17 - - U18 U19 W18 W19 - -"), # JA
73 Connector("pmod", 1, "Y14 W14 T10 T11 - - W16 V16 W13 V12 - -"), # JB
74
75 Connector("ck_io", 0, {
76 # Outer Digital Header
77 "io0": "T14",
78 "io1": "U12",
79 "io2": "U13",
80 "io3": "V13",
81 "io4": "V15",
82 "io5": "T15",
83 "io6": "R16",
84 "io7": "U17",
85 "io8": "V17",
86 "io9": "V18",
87 "io10": "T16",
88 "io11": "R17",
89 "io12": "P18",
90 "io13": "N17",
91
92 # Inner Digital Header
93 "io26": "U5",
94 "io27": "V5",
95 "io28": "V6",
96 "io29": "U7",
97 "io30": "V7",
98 "io31": "U8",
99 "io32": "V8",
100 "io33": "V10",
101 "io34": "W10",
102 "io35": "W6",
103 "io36": "Y6",
104 "io37": "Y7",
105 "io38": "W8",
106 "io39": "Y8",
107 "io40": "W9",
108 "io41": "Y9",
109
110 # Outer Analog Header as Digital IO
111 "a0": "Y11",
112 "a1": "Y12",
113 "a2": "W11",
114 "a3": "V11",
115 "a4": "T5",
116 "a5": "U10",
117
118 # Inner Analog Header as Digital IO
119 "a6": "F19",
120 "a7": "F20",
121 "a8": "C20",
122 "a9": "B20",
123 "a10": "B19",
124 "a11": "A20",
125
126 # Misc.
127 "a": "Y13"
128 }),
129
130 Connector("ck_spi", 0, {
131 "miso": "W15",
132 "mosi": "T12",
133 "sck": "H15",
134 "ss": "F16"
135 }),
136
137 Connector("ck_i2c", 0, {
138 "scl": "P16",
139 "sda": "P15"
140 }),
141
142 Connector("xadc", 0, {
143 # Outer Analog Header
144 "vaux1_n": "D18",
145 "vaux1_p": "E17",
146 "vaux9_n": "E19",
147 "vaux9_p": "E18",
148 "vaux6_n": "J14",
149 "vaux6_p": "K14",
150 "vaux15_n": "J16",
151 "vaux15_p": "K16",
152 "vaux5_n": "H20",
153 "vaux5_p": "J20",
154 "vaux13_n": "G20",
155 "vaux13_p": "G19",
156
157 # Inner Analog Header
158 "vaux12_n": "F20",
159 "vaux12_p": "F19",
160 "vaux0_n": "B20",
161 "vaux0_p": "C20",
162 "vaux8_n": "A20",
163 "vaux8_p": "B19"
164 })
165 ]
166
167 def toolchain_program(self, products, name, **kwargs):
168 xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
169 with products.extract("{}.bit".format(name)) as bitstream_filename:
170 subprocess.run([xc3sprog, "-c", "jtaghs1_fast", "-p", "1", bitstream_filename], check=True)
171
172
173 if __name__ == "__main__":
174 from .test.blinky import *
175 ArtyZ720Platform().build(Blinky(), do_program=True)