4 from nmigen
.build
import *
5 from nmigen
.vendor
.xilinx_7series
import *
6 from .resources
import *
9 __all__
= ["ArtyZ720Platform"]
12 class ArtyZ720Platform(Xilinx7SeriesPlatform
):
16 default_clk
= "clk125"
19 Pins("H16", dir="i"), Clock(125e6
), Attrs(IOSTANDARD
="LVCMOS33")),
23 attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
26 r
="N15", g
="G17", b
="L15", # LD4
27 attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
28 RGBLEDResource(1, # LD5
29 r
="M15", g
="L14", b
="G14",
30 attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
33 pins
="R14 P14 N16 M14",
34 attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
37 pins
="D19 D20 L20 L19",
38 attrs
=Attrs(IOSTANDARD
="LVCMOS33")),
41 Subsignal("pwm", Pins("R18", dir="o")),
42 Subsignal("sd", PinsN("T17", dir="o")),
43 Attrs(IOSTANDARD
="LVCMOS33")),
45 Resource("crypto_sda", 0, # ATSHA204A
46 Pins("J15", dir="io"),
47 Attrs(IOSTANDARD
="LVCMOS33")),
49 Resource("hdmi_rx", 0, # J10
50 Subsignal("cec", Pins("H17", dir="io")),
51 Subsignal("clk", DiffPairs("N18", "P19", dir="i"),
52 Attrs(IOSTANDARD
="TMDS_33")),
53 Subsignal("d", DiffPairs("V20 T20 N20", "W20 U20 P20", dir="i"),
54 Attrs(IOSTANDARD
="TMDS_33")),
55 Subsignal("hpd", Pins("T19", dir="o")),
56 Subsignal("scl", Pins("U14", dir="io")),
57 Subsignal("sda", Pins("U15", dir="io")),
58 Attrs(IOSTANDARD
="LVCMOS33")),
60 Resource("hdmi_tx", 0, # J11
61 Subsignal("cec", Pins("G15", dir="io")),
62 Subsignal("clk", DiffPairs("L16", "L17", dir="o"),
63 Attrs(IOSTANDARD
="TMDS_33")),
64 Subsignal("d", DiffPairs("K17 K19 J18", "K18 J19 H18", dir="o"),
65 Attrs(IOSTANDARD
="TMDS_33")),
66 Subsignal("hpd", PinsN("R19", dir="i")),
67 Subsignal("scl", Pins("M17", dir="io")),
68 Subsignal("sda", Pins("M18", dir="io")),
69 Attrs(IOSTANDARD
="LVCMOS33"))
72 Connector("pmod", 0, "Y18 Y19 Y16 Y17 - - U18 U19 W18 W19 - -"), # JA
73 Connector("pmod", 1, "Y14 W14 T10 T11 - - W16 V16 W13 V12 - -"), # JB
75 Connector("ck_io", 0, {
76 # Outer Digital Header
92 # Inner Digital Header
110 # Outer Analog Header as Digital IO
118 # Inner Analog Header as Digital IO
130 Connector("ck_spi", 0, {
137 Connector("ck_i2c", 0, {
142 Connector("xadc", 0, {
143 # Outer Analog Header
157 # Inner Analog Header
167 def toolchain_program(self
, products
, name
, **kwargs
):
168 xc3sprog
= os
.environ
.get("XC3SPROG", "xc3sprog")
169 with products
.extract("{}.bit".format(name
)) as bitstream_filename
:
170 subprocess
.run([xc3sprog
, "-c", "jtaghs1_fast", "-p", "1", bitstream_filename
], check
=True)
173 if __name__
== "__main__":
174 from .test
.blinky
import *
175 ArtyZ720Platform().build(Blinky(), do_program
=True)