4 from nmigen
.build
import *
5 from nmigen
.vendor
.altera
import *
6 from .resources
import *
9 __all__
= ["DE0Platform"]
12 class DE0Platform(AlteraPlatform
):
13 device
= "EP3C16" # Cyclone III 15K LEs
14 package
= "F484" # FBGA-484 UBGA-672
18 Resource("clk50", 0, Pins("G21", dir="i"),
19 Clock(50e6
), Attrs(io_standard
="3.3-V LVTTL")),
20 Resource("clk50", 1, Pins("B12", dir="i"),
21 Clock(50e6
), Attrs(io_standard
="3.3-V LVTTL")),
24 pins
="J1 J2 J3 H1 F2 E1 C1 C2 B2 B1",
25 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
28 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
30 pins
="J6 H5 H6 G4 G5 J7 H7 E3 E4 D2",
31 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
32 Display7SegResource(0,
33 a
="E11", b
="F11", c
="H12", d
="H13", e
="G12", f
="F12", g
="F13", dp
="D13", invert
=True,
34 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
35 Display7SegResource(1,
36 a
="A13", b
="B13", c
="C13", d
="A14", e
="B14", f
="E14", g
="A15", dp
="B15", invert
=True,
37 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
38 Display7SegResource(2,
39 a
="D15", b
="A16", c
="B16", d
="E15", e
="A17", f
="B17", g
="F14", dp
="A18", invert
=True,
40 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
41 Display7SegResource(3,
42 a
="B18", b
="F15", c
="A19", d
="B19", e
="C19", f
="D19", g
="G15", dp
="G16", invert
=True,
43 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
46 rx
="U22", tx
="U21", rts
="V22", cts
="V21",
47 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
49 Resource("display_hd44780", 0,
50 Subsignal("e", Pins("E21", dir="o")),
51 Subsignal("d", Pins("D22 D21 C22 C21 B22 B21 D20 C20", dir="io")),
52 Subsignal("rw", Pins("E22", dir="o")),
53 Subsignal("rs", Pins("F22", dir="o")),
55 Subsignal("bl", Pins("F21", dir="o")),
56 Attrs(io_standard
="3.3-V LVTTL")
60 Subsignal("r", Pins("H19 H17 H20 H21", dir="o")),
61 Subsignal("g", Pins("H22 J17 K17 J21", dir="o")),
62 Subsignal("b", Pins("K22 K21 J22 K18", dir="o")),
63 Subsignal("hs", Pins("L21", dir="o")),
64 Subsignal("vs", Pins("L22", dir="o")),
65 Attrs(io_standard
="3.3-V LVTTL")
68 Resource("ps2_host", 0, # Keyboard
69 Subsignal("clk", Pins("P22", dir="i")),
70 Subsignal("dat", Pins("P21", dir="io")),
71 Attrs(io_standard
="3.3-V LVTTL")
73 Resource("ps2_host", 1, # Mouse
74 Subsignal("clk", Pins("R21", dir="i")),
75 Subsignal("dat", Pins("R22", dir="io")),
76 Attrs(io_standard
="3.3-V LVTTL")
80 clk
="Y21", cmd
="Y22", dat0
="AA22", dat3
="W21", wp
="W20",
81 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
84 clk
="E5", cke
="E6", cs
="G7", we
="D6", ras
="F7", cas
="G8",
85 ba
="B5 A4", a
="C4 A3 B3 C3 A5 C6 B6 A6 C7 B7 B4 A7 C8",
86 dq
="D10 G10 H10 E9 F9 G9 H9 F8 A8 B9 A9 C10 B10 A10 E10 F10", dqm
="E7 B8",
87 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
91 cs
="N8", oe
="R6", we
="P4", wp
="T3", by
="M7",
92 a
="P7 P5 P6 N7 N5 N6 M8 M4 P2 N2 N1 M3 M2 M1 L7 L6 AA2 M5 M6 P1 P3 R2",
93 dq
="R7 P8 R8 U1 V2 V3 W1 Y1 T5 T7 T4 U2 V1 V4 W2 Y2",
94 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
98 "AB12 AB16 AA12 AA16 AA15 AB15 AA14 AB14 AB13 AA13 - - "
99 "AB10 AA10 AB8 AA8 AB5 AA5 AB3 AB4 AA3 AA4 V14 U14 "
100 "Y13 W13 U13 V12 - - R10 V11 Y10 W10 T8 V8 "
103 "AB11 AA20 AA11 AB20 AA19 AB19 AB18 AA18 AA17 AB17 - - "
104 "Y17 W17 U15 T15 W15 V15 R16 AB9 T16 AA9 AA7 AB7 "
105 "T14 R14 U12 T12 - - R11 R12 U10 T10 U9 T9 "
109 def toolchain_program(self
, products
, name
):
110 quartus_pgm
= os
.environ
.get("QUARTUS_PGM", "quartus_pgm")
111 with products
.extract("{}.sof".format(name
)) as bitstream_filename
:
112 subprocess
.check_call([quartus_pgm
, "--haltcc", "--mode", "JTAG",
113 "--operation", "P;" + bitstream_filename
])
116 if __name__
== "__main__":
117 from .test
.blinky
import Blinky
118 DE0Platform().build(Blinky(), do_program
=True)