4 from nmigen
.build
import *
5 from nmigen
.vendor
.intel
import *
6 from .resources
import *
9 __all__
= ["DE0CVPlatform"]
12 class DE0CVPlatform(IntelPlatform
):
13 device
= "5CEBA4" # Cyclone V 49K LEs
14 package
= "F23" # FBGA-484
18 Resource("clk50", 0, Pins("M9", dir="i"),
19 Clock(50e6
), Attrs(io_standard
="3.3-V LVTTL")),
20 Resource("clk50", 1, Pins("H13", dir="i"),
21 Clock(50e6
), Attrs(io_standard
="3.3-V LVTTL")),
22 Resource("clk50", 2, Pins("E10", dir="i"),
23 Clock(50e6
), Attrs(io_standard
="3.3-V LVTTL")),
24 Resource("clk50", 3, Pins("V15", dir="i"),
25 Clock(50e6
), Attrs(io_standard
="3.3-V LVTTL")),
28 pins
="AA2 AA1 W2 Y3 N2 N1 U2 U1 L2 L1", invert
=True,
29 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
31 pins
="U7 W9 M7 M6", invert
=True,
32 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
34 pins
="U13 V13 T13 T12 AA15 AB15 AA14 AA13 AB13 AB12",
35 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
36 Display7SegResource(0,
37 a
="U21", b
="V21", c
="W22", d
="W21", e
="Y22", f
="Y21", g
="AA22", invert
=True,
38 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
39 Display7SegResource(1,
40 a
="AA20", b
="AB20", c
="AA19", d
="AA18", e
="AB18", f
="AA17", g
="U22", invert
=True,
41 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
42 Display7SegResource(2,
43 a
="Y19", b
="AB17", c
="AA10", d
="Y14", e
="V14", f
="AB22", g
="AB21", invert
=True,
44 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
45 Display7SegResource(3,
46 a
="Y16", b
="W16", c
="Y17", d
="V16", e
="U17", f
="V18", g
="V19", invert
=True,
47 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
48 Display7SegResource(4,
49 a
="U20", b
="Y20", c
="V20", d
="U16", e
="U15", f
="Y15", g
="P9", invert
=True,
50 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
51 Display7SegResource(5,
52 a
="N9", b
="M8", c
="T14", d
="P14", e
="C1", f
="C2", g
="W19", invert
=True,
53 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
56 Subsignal("r", Pins("A9 B10 C9 A5", dir="o")),
57 Subsignal("g", Pins("L7 K7 J7 J8", dir="o")),
58 Subsignal("b", Pins("B6 B7 A8 A7", dir="o")),
59 Subsignal("hs", Pins("H8", dir="o")),
60 Subsignal("vs", Pins("G8", dir="o")),
61 Attrs(io_standard
="3.3-V LVTTL")
64 Resource("ps2_host", 0, # Keyboard
65 Subsignal("clk", Pins("D3", dir="i")),
66 Subsignal("dat", Pins("G2", dir="io")),
67 Attrs(io_standard
="3.3-V LVTTL")
69 Resource("ps2_host", 1, # Mouse
70 Subsignal("clk", Pins("E2", dir="i")),
71 Subsignal("dat", Pins("G1", dir="io")),
72 Attrs(io_standard
="3.3-V LVTTL")
76 clk
="H11", cmd
="B11", dat0
="K9", dat1
="D12", dat2
="E12", dat3
="C11", wp
="W20",
77 attrs
=Attrs(io_standard
="3.3-V LVTTL")),
80 clk
="AB11", cke
="R6", cs
="G7", we
="AB5", ras
="AB6", cas
="V6",
81 ba
="B5 A4", a
="W8 T8 U11 Y10 N6 AB10 P12 P7 P8 R5 U8 P6 R7",
82 dq
="Y9 T10 R9 Y11 R10 R11 R12 AA12 AA9 AB8 AA8 AA7 V10 V9 U10 T9", dqm
="U12 N8",
83 attrs
=Attrs(io_standard
="3.3-V LVCMOS")),
87 "N16 B16 M16 C16 D17 K20 K21 K22 M20 M21 "
88 "- - N21 R22 R21 T22 N20 N19 M22 P19 "
89 "L22 P17 P16 M18 L18 L17 L19 K17 - - "
90 "K19 P18 R15 R17 R16 T20 T19 T18 T17 T15 "),
92 "H16 A12 H15 B12 A13 B13 C13 D13 G18 G17 "
93 "- - H18 J18 J19 G11 H10 J11 H14 A15 "
94 "J13 L8 A14 B15 C15 E14 E15 E16 - - "
95 "F14 F15 F13 F12 G16 G15 G13 G12 J17 K16 "),
98 def toolchain_program(self
, products
, name
):
99 quartus_pgm
= os
.environ
.get("QUARTUS_PGM", "quartus_pgm")
100 with products
.extract("{}.sof".format(name
)) as bitstream_filename
:
101 subprocess
.check_call([quartus_pgm
, "--haltcc", "--mode", "JTAG",
102 "--operation", "P;" + bitstream_filename
])
105 if __name__
== "__main__":
106 from .test
.blinky
import Blinky
107 DE0CVPlatform().build(Blinky(), do_program
=True)