nmigen_boards/dev/sram.py

   1 from nmigen.build import *
   2
   3
   4 __all__ = ["SRAMResource"]
   5
   6
   7 def SRAMResource(*args, cs, oe=None, we, a, d, dm=None, attrs=None):
   8     io = []
   9     io.append(Subsignal("cs", PinsN(cs, dir="o", assert_width=1)))
  10     if oe is not None:
  11         # Asserted WE# deactivates the D output buffers, so WE# can be used to replace OE#.
  12         io.append(Subsignal("oe", PinsN(oe, dir="o", assert_width=1)))
  13     io.append(Subsignal("we", PinsN(we, dir="o", assert_width=1)))
  14     io.append(Subsignal("a", Pins(a, dir="o")))
  15     io.append(Subsignal("d", Pins(d, dir="io")))
  16     if dm is not None:
  17         io.append(Subsignal("dm", PinsN(dm, dir="o"))) # dm="LB# UB#"
  18     if attrs is not None:
  19         io.append(attrs)
  20     return Resource.family(*args, default_name="sram", ios=io)