nmigen_boards/dev/uart.py

   1 from nmigen.build import *
   2
   3
   4 __all__ = ["UARTResource", "IrDAResource"]
   5
   6
   7 def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
   8                  attrs=None):
   9     io = []
  10     io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
  11     io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
  12     if rts is not None:
  13         io.append(Subsignal("rts", Pins(rts, dir="o", assert_width=1)))
  14     if cts is not None:
  15         io.append(Subsignal("cts", Pins(cts, dir="i", assert_width=1)))
  16     if dtr is not None:
  17         io.append(Subsignal("dtr", Pins(dtr, dir="o", assert_width=1)))
  18     if dsr is not None:
  19         io.append(Subsignal("dsr", Pins(dsr, dir="i", assert_width=1)))
  20     if dcd is not None:
  21         io.append(Subsignal("dcd", Pins(dcd, dir="i", assert_width=1)))
  22     if ri is not None:
  23         io.append(Subsignal("ri", Pins(ri, dir="i", assert_width=1)))
  24     if attrs is not None:
  25         io.append(attrs)
  26     return Resource.family(*args, default_name="uart", ios=io)
  27
  28
  29 def IrDAResource(number, *, rx, tx, en=None, sd=None, attrs=None):
  30     # Exactly one of en (active-high enable) or sd (shutdown, active-low enable) should
  31     # be specified, and it is mapped to a logic level en subsignal.
  32     assert (en is not None) ^ (sd is not None)
  33     io = []
  34     io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
  35     io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
  36     if en is not None:
  37         io.append(Subsignal("en", Pins(en, dir="o", assert_width=1)))
  38     if sd is not None:
  39         io.append(Subsignal("en", PinsN(sd, dir="o", assert_width=1)))
  40     if attrs is not None:
  41         io.append(attrs)
  42     return Resource("irda", number, *io)