Add support for the iCE40-HX8K Breakout Board
[nmigen-boards.git] / nmigen_boards / ice40_hx8k_b_evn.py
1 import os
2 import subprocess
3
4 from nmigen.build import *
5 from nmigen.vendor.lattice_ice40 import *
6 from .dev import *
7
8
9 __all__ = ["ICE40HX8KBEVNPlatform"]
10
11
12 class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
13 device = "iCE40HX8K"
14 package = "CT256"
15 resources = [
16 Resource("clk12", 0, Pins("J3", dir="i"),
17 Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
18
19 Resource("user_led", 0, Pins("C3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D2
20 Resource("user_led", 1, Pins("B3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D3
21 Resource("user_led", 2, Pins("C4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D4
22 Resource("user_led", 3, Pins("C5", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D5
23 Resource("user_led", 4, Pins("A1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D6
24 Resource("user_led", 5, Pins("A2", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D7
25 Resource("user_led", 6, Pins("B4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D8
26 Resource("user_led", 7, Pins("B5", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS33")), # D9
27
28 UARTResource(0,
29 rx="B10", tx="B12", rts="B13", cts="A15", dtr="A16", dsr="B14", dcd="B15",
30 attrs=Attrs(IO_STANDARD="SB_LVCMOS33", PULLUP="1")
31 ),
32
33 *SPIFlashResources(0,
34 cs="R12", clk="R11", mosi="P12", miso="P11",
35 attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
36 ),
37 ]
38 connectors = [
39 Connector("j", 1, # J1
40 "A16 - A15 B15 B13 B14 - - B12 B11"
41 "A11 B10 A10 C9 - - A9 B9 B8 A7"
42 "B7 C7 - - A6 C6 B6 C5 A5 C4"
43 "- - B5 C3 B4 B3 A2 A1 - -"),
44 Connector("j", 2, # J2
45 "- - - R15 P16 P15 - - N16 M15"
46 "M16 L16 K15 K16 - - K14 J14 G14 F14"
47 "J15 H14 - - H16 G15 G16 F15 F16 E14"
48 "- - E16 D15 D16 D14 C16 B16 - -"),
49 Connector("j", 3, # J3
50 "R16 - T15 T16 T13 T14 - - N12 P13"
51 "N10 M11 T11 P10 - - T10 R10 P8 P9"
52 "T9 R9 - - T7 T8 T6 R6 T5 R5"
53 "- - R3 R4 R2 T3 T1 T2 - -"),
54 Connector("j", 4, # J4
55 "- - - R1 P1 P2 - - N3 N2"
56 "M2 M1 L3 L1 - - K3 K1 J2 J1"
57 "H2 J3 - - G2 H1 F2 G1 E2 F1"
58 "- - D1 D2 C1 C2 B1 B2 - -"),
59 ]
60
61 def toolchain_program(self, products, name):
62 iceprog = os.environ.get("ICEPROG", "iceprog")
63 with products.extract("{}.bin".format(name)) as bitstream_filename:
64 # TODO: this should be factored out and made customizable
65 subprocess.run([iceprog, "-S", bitstream_filename], check=True)
66
67
68 if __name__ == "__main__":
69 from ._blinky import build_and_program
70 build_and_program(ICE40HX8KBEVNPlatform, "clk12")