4 from nmigen
.build
import *
5 from nmigen
.vendor
.lattice_ice40
import *
6 from .resources
import *
9 __all__
= ["ICE40HX8KBEVNPlatform"]
12 class ICE40HX8KBEVNPlatform(LatticeICE40Platform
):
17 Resource("clk12", 0, Pins("J3", dir="i"),
18 Clock(12e6
), Attrs(GLOBAL
=True, IO_STANDARD
="SB_LVCMOS")),
21 pins
="C3 B3 C4 C5 A1 A2 B4 B5",
22 attrs
=Attrs(IO_STANDARD
="SB_LVCMOS")
26 rx
="B10", tx
="B12", rts
="B13", cts
="A15", dtr
="A16", dsr
="B14", dcd
="B15",
27 attrs
=Attrs(IO_STANDARD
="SB_LVCMOS", PULLUP
=1),
32 cs
="R12", clk
="R11", mosi
="P12", miso
="P11",
33 attrs
=Attrs(IO_STANDARD
="SB_LVCMOS")
37 Connector("j", 1, # J1
38 "A16 - A15 B15 B13 B14 - - B12 B11 "
39 "A11 B10 A10 C9 - - A9 B9 B8 A7 "
40 "B7 C7 - - A6 C6 B6 C5 A5 C4 "
41 "- - B5 C3 B4 B3 A2 A1 - - "),
42 Connector("j", 2, # J2
43 "- - - R15 P16 P15 - - N16 M15 "
44 "M16 L16 K15 K16 - - K14 J14 G14 F14 "
45 "J15 H14 - - H16 G15 G16 F15 F16 E14 "
46 "- - E16 D15 D16 D14 C16 B16 - - "),
47 Connector("j", 3, # J3
48 "R16 - T15 T16 T13 T14 - - N12 P13 "
49 "N10 M11 T11 P10 - - T10 R10 P8 P9 "
50 "T9 R9 - - T7 T8 T6 R6 T5 R5 "
51 "- - R3 R4 R2 T3 T1 T2 - - "),
52 Connector("j", 4, # J4
53 "- - - R1 P1 P2 - - N3 N2 "
54 "M2 M1 L3 L1 - - K3 K1 J2 J1 "
55 "H2 J3 - - G2 H1 F2 G1 E2 F1 "
56 "- - D1 D2 C1 C2 B1 B2 - - "),
59 def toolchain_program(self
, products
, name
):
60 iceprog
= os
.environ
.get("ICEPROG", "iceprog")
61 with products
.extract("{}.bin".format(name
)) as bitstream_filename
:
62 # TODO: this should be factored out and made customizable
63 subprocess
.check_call([iceprog
, "-S", bitstream_filename
])
66 if __name__
== "__main__":
67 from .test
.blinky
import *
68 ICE40HX8KBEVNPlatform().build(Blinky(), do_program
=True)