Fix IO_STANDARD on all iCE40 boards.
[nmigen-boards.git] / nmigen_boards / ice40_hx8k_b_evn.py
1 import os
2 import subprocess
3
4 from nmigen.build import *
5 from nmigen.vendor.lattice_ice40 import *
6 from .dev import *
7
8
9 __all__ = ["ICE40HX8KBEVNPlatform"]
10
11
12 class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
13 device = "iCE40HX8K"
14 package = "CT256"
15 default_clk = "clk12"
16 resources = [
17 Resource("clk12", 0, Pins("J3", dir="i"),
18 Clock(12e6), Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
19
20 Resource("user_led", 0, Pins("C3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D2
21 Resource("user_led", 1, Pins("B3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D3
22 Resource("user_led", 2, Pins("C4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D4
23 Resource("user_led", 3, Pins("C5", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D5
24 Resource("user_led", 4, Pins("A1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D6
25 Resource("user_led", 5, Pins("A2", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D7
26 Resource("user_led", 6, Pins("B4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D8
27 Resource("user_led", 7, Pins("B5", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")), # D9
28
29 UARTResource(0,
30 rx="B10", tx="B12", rts="B13", cts="A15", dtr="A16", dsr="B14", dcd="B15",
31 attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
32 ),
33
34 *SPIFlashResources(0,
35 cs="R12", clk="R11", mosi="P12", miso="P11",
36 attrs=Attrs(IO_STANDARD="SB_LVCMOS")
37 ),
38 ]
39 connectors = [
40 Connector("j", 1, # J1
41 "A16 - A15 B15 B13 B14 - - B12 B11 "
42 "A11 B10 A10 C9 - - A9 B9 B8 A7 "
43 "B7 C7 - - A6 C6 B6 C5 A5 C4 "
44 "- - B5 C3 B4 B3 A2 A1 - - "),
45 Connector("j", 2, # J2
46 "- - - R15 P16 P15 - - N16 M15 "
47 "M16 L16 K15 K16 - - K14 J14 G14 F14 "
48 "J15 H14 - - H16 G15 G16 F15 F16 E14 "
49 "- - E16 D15 D16 D14 C16 B16 - - "),
50 Connector("j", 3, # J3
51 "R16 - T15 T16 T13 T14 - - N12 P13 "
52 "N10 M11 T11 P10 - - T10 R10 P8 P9 "
53 "T9 R9 - - T7 T8 T6 R6 T5 R5 "
54 "- - R3 R4 R2 T3 T1 T2 - - "),
55 Connector("j", 4, # J4
56 "- - - R1 P1 P2 - - N3 N2 "
57 "M2 M1 L3 L1 - - K3 K1 J2 J1 "
58 "H2 J3 - - G2 H1 F2 G1 E2 F1 "
59 "- - D1 D2 C1 C2 B1 B2 - - "),
60 ]
61
62 def toolchain_program(self, products, name):
63 iceprog = os.environ.get("ICEPROG", "iceprog")
64 with products.extract("{}.bin".format(name)) as bitstream_filename:
65 # TODO: this should be factored out and made customizable
66 subprocess.check_call([iceprog, "-S", bitstream_filename])
67
68
69 if __name__ == "__main__":
70 from ._blinky import Blinky
71 ICE40HX8KBEVNPlatform().build(Blinky(), do_program=True)