nmigen_boards/nexys4ddr.py

   1 import os
   2 import subprocess
   3
   4 from nmigen.build import *
   5 from nmigen.vendor.xilinx_7series import *
   6 from .resources import *
   7
   8
   9 __all__ = ["Nexys4DDRPlatform"]
  10
  11
  12 class Nexys4DDRPlatform(Xilinx7SeriesPlatform):
  13     device      = "xc7a100t"
  14     package     = "csg324"
  15     speed       = "1"
  16     default_clk = "clk100"
  17     default_rst = "rst"
  18     resources   = [
  19         Resource("clk100", 0,
  20             Pins("E3", dir="i"), Clock(100e6), Attrs(IOSTANDARD="LVCMOS33")),
  21         Resource("rst", 0,
  22             PinsN("C12", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  23
  24         *SwitchResources(
  25             pins="J15 L16 M13 R15 R17 T18 U18 R13 T8  U8  R16 T13 H6  U12 U11 V10",
  26             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  27
  28         *LEDResources(
  29             pins="H17 K15 J13 N14 R18 V17 U17 U16 V16 T15 U14 T16 V15 V14 V12 V11",
  30             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  31
  32         RGBLEDResource(0,
  33             r="N15", g="M16", b="R12",
  34             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  35         RGBLEDResource(1,
  36             r="N16", g="R11", b="G14",
  37             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  38
  39         Display7SegResource(0,
  40             a="T10", b="R10", c="K16", d="K13", e="P15",
  41             f="T11", g="L18", dp="H15", invert=True,
  42             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  43         Resource("display_7seg_an", 0,
  44             PinsN("J17 J18 T9 J14 P14 T14 K2 U13", dir="o"),
  45             Attrs(IOSTANDARD="LVCMOS33")),
  46
  47         Resource("button_reset", 0,
  48             PinsN("C12", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  49         Resource("button_center", 0,
  50             Pins("N17",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  51         Resource("button_up", 0,
  52             Pins("M18",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  53         Resource("button_left", 0,
  54             Pins("P17",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  55         Resource("button_right", 0,
  56             Pins("M17",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  57         Resource("button_down", 0,
  58             Pins("P18",  dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
  59
  60         Resource("vga", 0,
  61             Subsignal("r",  Pins("A3 B4 C5 A4", dir="o")),
  62             Subsignal("g",  Pins("C6 A5 B6 A6", dir="o")),
  63             Subsignal("b",  Pins("B7 C7 D7 D8", dir="o")),
  64             Subsignal("hs", Pins("B11"        , dir="o")),
  65             Subsignal("vs", Pins("B12"        , dir="o")),
  66             Attrs(IOSTANDARD="LVCMOS33")),
  67
  68         *SDCardResources(0,
  69             clk="B1",  cmd="C1",  cd="A1",
  70             dat0="C2", dat1="E1", dat2="F1", dat3="D2",
  71             attrs=Attrs(IOSTANDARD="LVCMOS33")),
  72         Resource("sd_card_reset", 0,
  73             Pins("E2", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
  74
  75         Resource("accelerometer", 0,                        # ADXL362
  76             Subsignal("cs",   PinsN("D15",    dir="o")),
  77             Subsignal("clk",  Pins("F15",     dir="o")),
  78             Subsignal("mosi", Pins("F14",     dir="o")),
  79             Subsignal("miso", Pins("E15",     dir="i")),
  80             Subsignal("int",  Pins("B13 C16", dir="i"),
  81                 Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")),
  82             Attrs(IOSTANDARD="LVCMOS33")),
  83
  84         Resource("temp_sensor", 0,                          # ADT7420
  85             Subsignal("scl", Pins("C14", dir="o")),
  86             Subsignal("sda", Pins("C15", dir="io")),
  87             Subsignal("int", Pins("D13", dir="i"), Attrs(PULLUP="TRUE")),
  88             Subsignal("ct",  Pins("B14", dir="i"), Attrs(PULLUP="TRUE")),
  89             Attrs(IOSTANDARD="LVCMOS33")),
  90
  91         Resource("microphone", 0,                           # ADMP421
  92             Subsignal("clk",    Pins("J5", dir="o")),
  93             Subsignal("data",   Pins("H5", dir="i")),
  94             Subsignal("lr_sel", Pins("F5", dir="o")),
  95             Attrs(IOSTANDARD="LVCMOS33")),
  96
  97         Resource("audio", 0,
  98             Subsignal("pwm", Pins("A11",  dir="o")),
  99             Subsignal("sd",  PinsN("D12", dir="o")),
 100             Attrs(IOSTANDARD="LVCMOS33")),
 101
 102         UARTResource(0,
 103             rx="C4", tx="D4", rts="D3", cts="E5",
 104             attrs=Attrs(IOSTANDARD="LVCMOS33")),
 105
 106         Resource("ps2_host", 0,
 107             Subsignal("clk", Pins("F4", dir="i")),
 108             Subsignal("dat", Pins("B2", dir="io")),
 109             Attrs(IOSTANDARD="LVCMOS33", PULLUP="TRUE")),
 110
 111         Resource("eth", 0,                                  # LAN8720A
 112             Subsignal("mdio",   Pins("A9",      dir="io")),
 113             Subsignal("mdc",    Pins("C9",      dir="o")),
 114             Subsignal("reset",  Pins("B3",      dir="o")),
 115             Subsignal("rxd",    Pins("C11 D10", dir="io")),
 116             Subsignal("rxerr",  Pins("C10",     dir="io")),
 117             Subsignal("txd",    Pins("A10 A8",  dir="o")),
 118             Subsignal("txen",   Pins("B9",      dir="o")),
 119             Subsignal("crs_dv", Pins("D9",      dir="io")),
 120             Subsignal("int",    PinsN("B8",     dir="io")),
 121             Subsignal("clk",    Pins("D5",      dir="o"), Clock(50e6)),
 122             Attrs(IOSTANDARD="LVCMOS33")),
 123
 124         *SPIFlashResources(0,
 125             cs="L13", clk="E9", mosi="K17", miso="K18", wp="L14", hold="M14",
 126             attrs=Attrs(IOSTANDARD="LVCMOS33")),
 127
 128         Resource("ddr2", 0,                                 # MT47H64M16HR-25:H
 129             Subsignal("a",
 130                 Pins("M4 P4 M6 T1 L3 P5 M2 N1 L4 N5 R2 K5 N6 K3", dir="o")),
 131             Subsignal("dq",
 132                 Pins("R7 V6 R8 U7 V7 R6 U6 R5 T5 U3 V5 U4 V4 T4 V1 T3", dir="io"),
 133                     Attrs(IN_TERM="UNTUNED_SPLIT_50")),
 134             Subsignal("ba",  Pins("P2 P3 R1", dir="o")),
 135             Subsignal("clk", DiffPairs("L6", "L5", dir="o"),
 136                 Attrs(IOSTANDARD="DIFF_SSTL18_I")),
 137             Subsignal("clk_en", Pins("M1", dir="o")),
 138             Subsignal("cs",  PinsN("K6", dir="o")),
 139             Subsignal("we",  PinsN("N2", dir="o")),
 140             Subsignal("ras", PinsN("N4", dir="o")),
 141             Subsignal("cas", PinsN("L1", dir="o")),
 142             Subsignal("dqs", DiffPairs("U9 U2", "V9 V2", dir="o"),
 143                 Attrs(IOSTANDARD="DIFF_SSTL18_I")),
 144             Subsignal("dm",  Pins("T6 U1", dir="o")),
 145             Subsignal("odt", Pins("R5",    dir="o")),
 146             Attrs(IOSTANDARD="SSTL18_I", SLEW="FAST"))
 147     ]
 148     connectors = [
 149         Connector("pmod", 0, "C17 D18 E18 G17 - - D17 E17 F18 G18 - -"),  # JA
 150         Connector("pmod", 1, "D14 F16 G16 H14 - - E16 F13 G13 H16 - -"),  # JB
 151         Connector("pmod", 2, "K1  F6  J2  G6  - - E7  J3  J4  E6  - -"),  # JC
 152         Connector("pmod", 3, "H4  H1  G1  G3  - - H2  G4  G2  F3  - -")   # JD
 153     ]
 154
 155     def toolchain_prepare(self, fragment, name, **kwargs):
 156         overrides = {
 157             "script_before_bitstream":
 158                 "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
 159             "script_after_bitstream":
 160                 "write_cfgmem -force -format bin -interface spix4 -size 16 "
 161                 "-loadbit \"up 0x0 {name}.bit\" -file {name}.bin".format(name=name),
 162             "add_constraints":
 163                 """
 164                 set_property INTERNAL_VREF 0.9 [get_iobanks 34]
 165                 set_property CFGBVS VCCO [current_design]
 166                 set_property CONFIG_VOLTAGE 3.3 [current_design]
 167                 """
 168         }
 169         return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
 170
 171     def toolchain_program(self, products, name):
 172         xc3sprog = os.environ.get("XC3SPROG", "xc3sprog")
 173         with products.extract("{}.bit".format(name)) as bitstream_filename:
 174             subprocess.run([xc3sprog, "-c", "nexys4", bitstream_filename], check=True)
 175
 176
 177 if __name__ == "__main__":
 178     from .test.blinky import *
 179     Nexys4DDRPlatform().build(Blinky(), do_program=True)